startup_stm32f042.s 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341
  1. ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
  2. ;* File Name : startup_stm32f042.s
  3. ;* Author : MCD Appl&ication Team
  4. ;* Version : V1.5.0
  5. ;* Date : 24-December-2014
  6. ;* Description : STM32F042 Devices Devices vector table for
  7. ;* EWARM toolchain.
  8. ;* This module performs:
  9. ;* - Set the initial SP
  10. ;* - Set the initial PC == iar_program_start,
  11. ;* - Set the vector table entries with the exceptions ISR
  12. ;* address.
  13. ;* After Reset the Cortex-M0 processor is in Thread mode,
  14. ;* priority is Privileged, and the Stack is set to Main.
  15. ;*******************************************************************************
  16. ; @attention
  17. ;
  18. ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  19. ; You may not use this file except in compliance with the License.
  20. ; You may obtain a copy of the License at:
  21. ;
  22. ; http://www.st.com/software_license_agreement_liberty_v2
  23. ;
  24. ; Unless required by applicable law or agreed to in writing, software
  25. ; distributed under the License is distributed on an "AS IS" BASIS,
  26. ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  27. ; See the License for the specific language governing permissions and
  28. ; limitations under the License.
  29. ;
  30. ;*******************************************************************************
  31. ;
  32. ;
  33. ; The modules in this file are included in the libraries, and may be replaced
  34. ; by any user-defined modules that define the PUBLIC symbol _program_start or
  35. ; a user defined start symbol.
  36. ; To override the cstartup defined in the library, simply add your modified
  37. ; version to the workbench project.
  38. ;
  39. ; The vector table is normally located at address 0.
  40. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  41. ; The name "__vector_table" has special meaning for C-SPY:
  42. ; it is where the SP start value is found, and the NVIC vector
  43. ; table register (VTOR) is initialized to this address if != 0.
  44. ;
  45. ; Cortex-M version
  46. ;
  47. MODULE ?cstartup
  48. ;; Forward declaration of sections.
  49. SECTION CSTACK:DATA:NOROOT(3)
  50. SECTION .intvec:CODE:NOROOT(2)
  51. EXTERN __iar_program_start
  52. EXTERN SystemInit
  53. PUBLIC __vector_table
  54. DATA
  55. __vector_table
  56. DCD sfe(CSTACK)
  57. DCD Reset_Handler ; Reset Handler
  58. DCD NMI_Handler ; NMI Handler
  59. DCD HardFault_Handler ; Hard Fault Handler
  60. DCD 0 ; Reserved
  61. DCD 0 ; Reserved
  62. DCD 0 ; Reserved
  63. DCD 0 ; Reserved
  64. DCD 0 ; Reserved
  65. DCD 0 ; Reserved
  66. DCD 0 ; Reserved
  67. DCD SVC_Handler ; SVCall Handler
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD PendSV_Handler ; PendSV Handler
  71. DCD SysTick_Handler ; SysTick Handler
  72. ; External Interrupts
  73. DCD WWDG_IRQHandler ; Window Watchdog
  74. DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
  75. DCD RTC_IRQHandler ; RTC through EXTI Line
  76. DCD FLASH_IRQHandler ; FLASH
  77. DCD RCC_CRS_IRQHandler ; RCC and CRS
  78. DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
  79. DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
  80. DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
  81. DCD TSC_IRQHandler ; TS
  82. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  83. DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
  84. DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
  85. DCD ADC1_IRQHandler ; ADC1
  86. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
  87. DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
  88. DCD TIM2_IRQHandler ; TIM2
  89. DCD TIM3_IRQHandler ; TIM3
  90. DCD 0 ; Reserved
  91. DCD 0 ; Reserved
  92. DCD TIM14_IRQHandler ; TIM14
  93. DCD 0 ; Reserved
  94. DCD TIM16_IRQHandler ; TIM16
  95. DCD TIM17_IRQHandler ; TIM17
  96. DCD I2C1_IRQHandler ; I2C1
  97. DCD 0 ; Reserved
  98. DCD SPI1_IRQHandler ; SPI1
  99. DCD SPI2_IRQHandler ; SPI2
  100. DCD USART1_IRQHandler ; USART1
  101. DCD USART2_IRQHandler ; USART2
  102. DCD 0 ; Reserved
  103. DCD CEC_CAN_IRQHandler ; CEC and CAN
  104. DCD USB_IRQHandler ; USB
  105. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  106. ;;
  107. ;; Default interrupt handlers.
  108. ;;
  109. THUMB
  110. PUBWEAK Reset_Handler
  111. SECTION .text:CODE:NOROOT:REORDER(2)
  112. Reset_Handler
  113. LDR R0, =sfe(CSTACK) ; set stack pointer
  114. MSR MSP, R0
  115. ;;Check if boot space corresponds to test memory
  116. LDR R0,=0x00000004
  117. LDR R1, [R0]
  118. LSRS R1, R1, #24
  119. LDR R2,=0x1F
  120. CMP R1, R2
  121. BNE ApplicationStart
  122. ;; SYSCFG clock enable
  123. LDR R0,=0x40021018
  124. LDR R1,=0x00000001
  125. STR R1, [R0]
  126. ;; Set CFGR1 register with flash memory remap at address 0
  127. LDR R0,=0x40010000
  128. LDR R1,=0x00000000
  129. STR R1, [R0]
  130. ApplicationStart
  131. LDR R0, =SystemInit
  132. BLX R0
  133. LDR R0, =__iar_program_start
  134. BX R0
  135. PUBWEAK NMI_Handler
  136. SECTION .text:CODE:NOROOT:REORDER(1)
  137. NMI_Handler
  138. B NMI_Handler
  139. PUBWEAK HardFault_Handler
  140. SECTION .text:CODE:NOROOT:REORDER(1)
  141. HardFault_Handler
  142. B HardFault_Handler
  143. PUBWEAK SVC_Handler
  144. SECTION .text:CODE:NOROOT:REORDER(1)
  145. SVC_Handler
  146. B SVC_Handler
  147. PUBWEAK PendSV_Handler
  148. SECTION .text:CODE:NOROOT:REORDER(1)
  149. PendSV_Handler
  150. B PendSV_Handler
  151. PUBWEAK SysTick_Handler
  152. SECTION .text:CODE:NOROOT:REORDER(1)
  153. SysTick_Handler
  154. B SysTick_Handler
  155. PUBWEAK WWDG_IRQHandler
  156. SECTION .text:CODE:NOROOT:REORDER(1)
  157. WWDG_IRQHandler
  158. B WWDG_IRQHandler
  159. PUBWEAK PVD_VDDIO2_IRQHandler
  160. SECTION .text:CODE:NOROOT:REORDER(1)
  161. PVD_VDDIO2_IRQHandler
  162. B PVD_VDDIO2_IRQHandler
  163. PUBWEAK RTC_IRQHandler
  164. SECTION .text:CODE:NOROOT:REORDER(1)
  165. RTC_IRQHandler
  166. B RTC_IRQHandler
  167. PUBWEAK FLASH_IRQHandler
  168. SECTION .text:CODE:NOROOT:REORDER(1)
  169. FLASH_IRQHandler
  170. B FLASH_IRQHandler
  171. PUBWEAK RCC_CRS_IRQHandler
  172. SECTION .text:CODE:NOROOT:REORDER(1)
  173. RCC_CRS_IRQHandler
  174. B RCC_CRS_IRQHandler
  175. PUBWEAK EXTI0_1_IRQHandler
  176. SECTION .text:CODE:NOROOT:REORDER(1)
  177. EXTI0_1_IRQHandler
  178. B EXTI0_1_IRQHandler
  179. PUBWEAK EXTI2_3_IRQHandler
  180. SECTION .text:CODE:NOROOT:REORDER(1)
  181. EXTI2_3_IRQHandler
  182. B EXTI2_3_IRQHandler
  183. PUBWEAK EXTI4_15_IRQHandler
  184. SECTION .text:CODE:NOROOT:REORDER(1)
  185. EXTI4_15_IRQHandler
  186. B EXTI4_15_IRQHandler
  187. PUBWEAK TSC_IRQHandler
  188. SECTION .text:CODE:NOROOT:REORDER(1)
  189. TSC_IRQHandler
  190. B TSC_IRQHandler
  191. PUBWEAK DMA1_Channel1_IRQHandler
  192. SECTION .text:CODE:NOROOT:REORDER(1)
  193. DMA1_Channel1_IRQHandler
  194. B DMA1_Channel1_IRQHandler
  195. PUBWEAK DMA1_Channel2_3_IRQHandler
  196. SECTION .text:CODE:NOROOT:REORDER(1)
  197. DMA1_Channel2_3_IRQHandler
  198. B DMA1_Channel2_3_IRQHandler
  199. PUBWEAK DMA1_Channel4_5_IRQHandler
  200. SECTION .text:CODE:NOROOT:REORDER(1)
  201. DMA1_Channel4_5_IRQHandler
  202. B DMA1_Channel4_5_IRQHandler
  203. PUBWEAK ADC1_IRQHandler
  204. SECTION .text:CODE:NOROOT:REORDER(1)
  205. ADC1_IRQHandler
  206. B ADC1_IRQHandler
  207. PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
  208. SECTION .text:CODE:NOROOT:REORDER(1)
  209. TIM1_BRK_UP_TRG_COM_IRQHandler
  210. B TIM1_BRK_UP_TRG_COM_IRQHandler
  211. PUBWEAK TIM1_CC_IRQHandler
  212. SECTION .text:CODE:NOROOT:REORDER(1)
  213. TIM1_CC_IRQHandler
  214. B TIM1_CC_IRQHandler
  215. PUBWEAK TIM2_IRQHandler
  216. SECTION .text:CODE:NOROOT:REORDER(1)
  217. TIM2_IRQHandler
  218. B TIM2_IRQHandler
  219. PUBWEAK TIM3_IRQHandler
  220. SECTION .text:CODE:NOROOT:REORDER(1)
  221. TIM3_IRQHandler
  222. B TIM3_IRQHandler
  223. PUBWEAK TIM14_IRQHandler
  224. SECTION .text:CODE:NOROOT:REORDER(1)
  225. TIM14_IRQHandler
  226. B TIM14_IRQHandler
  227. PUBWEAK TIM16_IRQHandler
  228. SECTION .text:CODE:NOROOT:REORDER(1)
  229. TIM16_IRQHandler
  230. B TIM16_IRQHandler
  231. PUBWEAK TIM17_IRQHandler
  232. SECTION .text:CODE:NOROOT:REORDER(1)
  233. TIM17_IRQHandler
  234. B TIM17_IRQHandler
  235. PUBWEAK I2C1_IRQHandler
  236. SECTION .text:CODE:NOROOT:REORDER(1)
  237. I2C1_IRQHandler
  238. B I2C1_IRQHandler
  239. PUBWEAK SPI1_IRQHandler
  240. SECTION .text:CODE:NOROOT:REORDER(1)
  241. SPI1_IRQHandler
  242. B SPI1_IRQHandler
  243. PUBWEAK SPI2_IRQHandler
  244. SECTION .text:CODE:NOROOT:REORDER(1)
  245. SPI2_IRQHandler
  246. B SPI2_IRQHandler
  247. PUBWEAK USART1_IRQHandler
  248. SECTION .text:CODE:NOROOT:REORDER(1)
  249. USART1_IRQHandler
  250. B USART1_IRQHandler
  251. PUBWEAK USART2_IRQHandler
  252. SECTION .text:CODE:NOROOT:REORDER(1)
  253. USART2_IRQHandler
  254. B USART2_IRQHandler
  255. PUBWEAK CEC_CAN_IRQHandler
  256. SECTION .text:CODE:NOROOT:REORDER(1)
  257. CEC_CAN_IRQHandler
  258. B CEC_CAN_IRQHandler
  259. PUBWEAK USB_IRQHandler
  260. SECTION .text:CODE:NOROOT:REORDER(1)
  261. USB_IRQHandler
  262. B USB_IRQHandler
  263. END
  264. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****