startup_stm32f030xc.s 10 KB

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  1. ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
  2. ;* File Name : startup_stm32f030xc.s
  3. ;* Author : MCD Application Team
  4. ;* Version : V1.5.0
  5. ;* Date : 24-December-2014
  6. ;* Description : STM32F030xC devices vector table for EWARM toolchain.
  7. ;* This module performs:
  8. ;* - Set the initial SP
  9. ;* - Set the initial PC == __iar_program_start,
  10. ;* - Set the vector table entries with the exceptions ISR
  11. ;* address.
  12. ;* After Reset the Cortex-M0 processor is in Thread mode,
  13. ;* priority is Privileged, and the Stack is set to Main.
  14. ;*******************************************************************************
  15. ; @attention
  16. ;
  17. ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  18. ; You may not use this file except in compliance with the License.
  19. ; You may obtain a copy of the License at:
  20. ;
  21. ; http://www.st.com/software_license_agreement_liberty_v2
  22. ;
  23. ; Unless required by applicable law or agreed to in writing, software
  24. ; distributed under the License is distributed on an "AS IS" BASIS,
  25. ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  26. ; See the License for the specific language governing permissions and
  27. ; limitations under the License.
  28. ;
  29. ;*******************************************************************************
  30. ;
  31. ;
  32. ; The modules in this file are included in the libraries, and may be replaced
  33. ; by any user-defined modules that define the PUBLIC symbol _program_start or
  34. ; a user defined start symbol.
  35. ; To override the cstartup defined in the library, simply add your modified
  36. ; version to the workbench project.
  37. ;
  38. ; The vector table is normally located at address 0.
  39. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  40. ; The name "__vector_table" has special meaning for C-SPY:
  41. ; it is where the SP start value is found, and the NVIC vector
  42. ; table register (VTOR) is initialized to this address if != 0.
  43. ;
  44. ; Cortex-M version
  45. ;
  46. MODULE ?cstartup
  47. ;; Forward declaration of sections.
  48. SECTION CSTACK:DATA:NOROOT(3)
  49. SECTION .intvec:CODE:NOROOT(2)
  50. EXTERN __iar_program_start
  51. EXTERN SystemInit
  52. PUBLIC __vector_table
  53. DATA
  54. __vector_table
  55. DCD sfe(CSTACK)
  56. DCD Reset_Handler ; Reset Handler
  57. DCD NMI_Handler ; NMI Handler
  58. DCD HardFault_Handler ; Hard Fault Handler
  59. DCD 0 ; Reserved
  60. DCD 0 ; Reserved
  61. DCD 0 ; Reserved
  62. DCD 0 ; Reserved
  63. DCD 0 ; Reserved
  64. DCD 0 ; Reserved
  65. DCD 0 ; Reserved
  66. DCD SVC_Handler ; SVCall Handler
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD PendSV_Handler ; PendSV Handler
  70. DCD SysTick_Handler ; SysTick Handler
  71. ; External Interrupts
  72. DCD WWDG_IRQHandler ; Window Watchdog
  73. DCD 0 ; Reserved
  74. DCD RTC_IRQHandler ; RTC through EXTI Line
  75. DCD FLASH_IRQHandler ; FLASH
  76. DCD RCC_IRQHandler ; RCC
  77. DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
  78. DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
  79. DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
  80. DCD 0 ; Reserved
  81. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  82. DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
  83. DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
  84. DCD ADC1_IRQHandler ; ADC1
  85. DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
  86. DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
  87. DCD 0 ; Reserved
  88. DCD TIM3_IRQHandler ; TIM3
  89. DCD TIM6_IRQHandler ; TIM6
  90. DCD TIM7_IRQHandler ; TIM7
  91. DCD TIM14_IRQHandler ; TIM14
  92. DCD TIM15_IRQHandler ; TIM15
  93. DCD TIM16_IRQHandler ; TIM16
  94. DCD TIM17_IRQHandler ; TIM17
  95. DCD I2C1_IRQHandler ; I2C1
  96. DCD I2C2_IRQHandler ; I2C2
  97. DCD SPI1_IRQHandler ; SPI1
  98. DCD SPI2_IRQHandler ; SPI2
  99. DCD USART1_IRQHandler ; USART1
  100. DCD USART2_IRQHandler ; USART2
  101. DCD USART3_6_IRQHandler ; USART3, USART4, USART5, USART6
  102. DCD 0 ; Reserved
  103. DCD 0 ; Reserved
  104. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  105. ;;
  106. ;; Default interrupt handlers.
  107. ;;
  108. THUMB
  109. PUBWEAK Reset_Handler
  110. SECTION .text:CODE:NOROOT:REORDER(2)
  111. Reset_Handler
  112. LDR R0, =sfe(CSTACK) ; set stack pointer
  113. MSR MSP, R0
  114. ;;Check if boot space corresponds to test memory
  115. LDR R0,=0x00000004
  116. LDR R1, [R0]
  117. LSRS R1, R1, #24
  118. LDR R2,=0x1F
  119. CMP R1, R2
  120. BNE ApplicationStart
  121. ;; SYSCFG clock enable
  122. LDR R0,=0x40021018
  123. LDR R1,=0x00000001
  124. STR R1, [R0]
  125. ;; Set CFGR1 register with flash memory remap at address 0
  126. LDR R0,=0x40010000
  127. LDR R1,=0x00000000
  128. STR R1, [R0]
  129. ApplicationStart
  130. LDR R0, =SystemInit
  131. BLX R0
  132. LDR R0, =__iar_program_start
  133. BX R0
  134. PUBWEAK NMI_Handler
  135. SECTION .text:CODE:NOROOT:REORDER(1)
  136. NMI_Handler
  137. B NMI_Handler
  138. PUBWEAK HardFault_Handler
  139. SECTION .text:CODE:NOROOT:REORDER(1)
  140. HardFault_Handler
  141. B HardFault_Handler
  142. PUBWEAK SVC_Handler
  143. SECTION .text:CODE:NOROOT:REORDER(1)
  144. SVC_Handler
  145. B SVC_Handler
  146. PUBWEAK PendSV_Handler
  147. SECTION .text:CODE:NOROOT:REORDER(1)
  148. PendSV_Handler
  149. B PendSV_Handler
  150. PUBWEAK SysTick_Handler
  151. SECTION .text:CODE:NOROOT:REORDER(1)
  152. SysTick_Handler
  153. B SysTick_Handler
  154. PUBWEAK WWDG_IRQHandler
  155. SECTION .text:CODE:NOROOT:REORDER(1)
  156. WWDG_IRQHandler
  157. B WWDG_IRQHandler
  158. PUBWEAK RTC_IRQHandler
  159. SECTION .text:CODE:NOROOT:REORDER(1)
  160. RTC_IRQHandler
  161. B RTC_IRQHandler
  162. PUBWEAK FLASH_IRQHandler
  163. SECTION .text:CODE:NOROOT:REORDER(1)
  164. FLASH_IRQHandler
  165. B FLASH_IRQHandler
  166. PUBWEAK RCC_IRQHandler
  167. SECTION .text:CODE:NOROOT:REORDER(1)
  168. RCC_IRQHandler
  169. B RCC_IRQHandler
  170. PUBWEAK EXTI0_1_IRQHandler
  171. SECTION .text:CODE:NOROOT:REORDER(1)
  172. EXTI0_1_IRQHandler
  173. B EXTI0_1_IRQHandler
  174. PUBWEAK EXTI2_3_IRQHandler
  175. SECTION .text:CODE:NOROOT:REORDER(1)
  176. EXTI2_3_IRQHandler
  177. B EXTI2_3_IRQHandler
  178. PUBWEAK EXTI4_15_IRQHandler
  179. SECTION .text:CODE:NOROOT:REORDER(1)
  180. EXTI4_15_IRQHandler
  181. B EXTI4_15_IRQHandler
  182. PUBWEAK DMA1_Channel1_IRQHandler
  183. SECTION .text:CODE:NOROOT:REORDER(1)
  184. DMA1_Channel1_IRQHandler
  185. B DMA1_Channel1_IRQHandler
  186. PUBWEAK DMA1_Channel2_3_IRQHandler
  187. SECTION .text:CODE:NOROOT:REORDER(1)
  188. DMA1_Channel2_3_IRQHandler
  189. B DMA1_Channel2_3_IRQHandler
  190. PUBWEAK DMA1_Channel4_5_IRQHandler
  191. SECTION .text:CODE:NOROOT:REORDER(1)
  192. DMA1_Channel4_5_IRQHandler
  193. B DMA1_Channel4_5_IRQHandler
  194. PUBWEAK ADC1_IRQHandler
  195. SECTION .text:CODE:NOROOT:REORDER(1)
  196. ADC1_IRQHandler
  197. B ADC1_IRQHandler
  198. PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
  199. SECTION .text:CODE:NOROOT:REORDER(1)
  200. TIM1_BRK_UP_TRG_COM_IRQHandler
  201. B TIM1_BRK_UP_TRG_COM_IRQHandler
  202. PUBWEAK TIM1_CC_IRQHandler
  203. SECTION .text:CODE:NOROOT:REORDER(1)
  204. TIM1_CC_IRQHandler
  205. B TIM1_CC_IRQHandler
  206. PUBWEAK TIM3_IRQHandler
  207. SECTION .text:CODE:NOROOT:REORDER(1)
  208. TIM3_IRQHandler
  209. B TIM3_IRQHandler
  210. PUBWEAK TIM6_IRQHandler
  211. SECTION .text:CODE:NOROOT:REORDER(1)
  212. TIM6_IRQHandler
  213. B TIM6_IRQHandler
  214. PUBWEAK TIM7_IRQHandler
  215. SECTION .text:CODE:NOROOT:REORDER(1)
  216. TIM7_IRQHandler
  217. B TIM7_IRQHandler
  218. PUBWEAK TIM14_IRQHandler
  219. SECTION .text:CODE:NOROOT:REORDER(1)
  220. TIM14_IRQHandler
  221. B TIM14_IRQHandler
  222. PUBWEAK TIM15_IRQHandler
  223. SECTION .text:CODE:NOROOT:REORDER(1)
  224. TIM15_IRQHandler
  225. B TIM15_IRQHandler
  226. PUBWEAK TIM16_IRQHandler
  227. SECTION .text:CODE:NOROOT:REORDER(1)
  228. TIM16_IRQHandler
  229. B TIM16_IRQHandler
  230. PUBWEAK TIM17_IRQHandler
  231. SECTION .text:CODE:NOROOT:REORDER(1)
  232. TIM17_IRQHandler
  233. B TIM17_IRQHandler
  234. PUBWEAK I2C1_IRQHandler
  235. SECTION .text:CODE:NOROOT:REORDER(1)
  236. I2C1_IRQHandler
  237. B I2C1_IRQHandler
  238. PUBWEAK I2C2_IRQHandler
  239. SECTION .text:CODE:NOROOT:REORDER(1)
  240. I2C2_IRQHandler
  241. B I2C2_IRQHandler
  242. PUBWEAK SPI1_IRQHandler
  243. SECTION .text:CODE:NOROOT:REORDER(1)
  244. SPI1_IRQHandler
  245. B SPI1_IRQHandler
  246. PUBWEAK SPI2_IRQHandler
  247. SECTION .text:CODE:NOROOT:REORDER(1)
  248. SPI2_IRQHandler
  249. B SPI2_IRQHandler
  250. PUBWEAK USART1_IRQHandler
  251. SECTION .text:CODE:NOROOT:REORDER(1)
  252. USART1_IRQHandler
  253. B USART1_IRQHandler
  254. PUBWEAK USART2_IRQHandler
  255. SECTION .text:CODE:NOROOT:REORDER(1)
  256. USART2_IRQHandler
  257. B USART2_IRQHandler
  258. PUBWEAK USART3_6_IRQHandler
  259. SECTION .text:CODE:NOROOT:REORDER(1)
  260. USART3_6_IRQHandler
  261. B USART3_6_IRQHandler
  262. END
  263. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****