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fd9a7cdb280a7f28e4a49bda9ae24f5332bf7bac.svn-base

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  1. #ifndef  __N76_SFR_H__
    2. 

  2. #define  __N76_SFR_H__
    3. 

  3. 

  4. /**** P0		80H *****/
    5. 

  5. #define set_P00			P00		=		1
    6. 

  6. #define set_P01			P01		=		1
    7. 

  7. #define set_P02			P02		=		1
    8. 

  8. #define set_P03			P03		=		1
    9. 

  9. #define set_P04			P04		=		1
    10. 

  10. #define set_P05			P05		=		1
    11. 

  11. #define set_P06			P06		=		1
    12. 

  12. #define set_P07			P07		=		1
    13. 

  13. 

  14. #define clr_P00			P00		=		0
    15. 

  15. #define clr_P01			P01		=		0
    16. 

  16. #define clr_P02			P02		=		0
    17. 

  17. #define clr_P03			P03		=		0
    18. 

  18. #define clr_P04			P04		=		0
    19. 

  19. #define clr_P05			P05		=		0
    20. 

  20. #define clr_P06			P06		=		0
    21. 

  21. #define clr_P07			P07		=		0
    22. 

  22. 

  23. //**** SP  	81H **** 
    24. 

  24. //**** DPH  82H **** 
    25. 

  25. //**** DPL  83H **** 
    26. 

  26. //**** RWK  86H **** 
    27. 

  27. 

  28. //**** PCON	87H *****
    29. 

  29. #define set_SMOD    PCON    |= SET_BIT7
    30. 

  30. #define set_SMOD0   PCON    |= SET_BIT6
    31. 

  31. #define set_POF     PCON    |= SET_BIT4
    32. 

  32. #define set_GF1     PCON    |= SET_BIT3
    33. 

  33. #define set_GF0     PCON    |= SET_BIT2 
    34. 

  34. #define set_PD      PCON    |= SET_BIT1
    35. 

  35. #define set_IDL    	PCON    |= SET_BIT0
    36. 

  36.                             
    37. 

  37. #define clr_SMOD    PCON    &= ~SET_BIT7
    38. 

  38. #define clr_SMOD0   PCON    &= ~SET_BIT6
    39. 

  39. #define clr_POF     PCON    &= ~SET_BIT4
    40. 

  40. #define clr_GF1     PCON    &= ~SET_BIT3
    41. 

  41. #define clr_GF0     PCON    &= ~SET_BIT2 
    42. 

  42. #define clr_PD      PCON    &= ~SET_BIT1
    43. 

  43. #define clr_IDL    	PCON    &= ~SET_BIT0
    44. 

  44. 

  45. /**** TCON		88H ****/
    46. 

  46. #define set_TF1			TF1		=		1
    47. 

  47. #define set_TR1			TR1		=		1
    48. 

  48. #define set_TF0			TF0		=		1
    49. 

  49. #define set_TR0			TR0		=		1
    50. 

  50. #define set_IE1			IE1		=		1
    51. 

  51. #define set_IT1			IT1		=		1
    52. 

  52. #define set_IE0			IE0		=		1
    53. 

  53. #define set_IT0			IT0		=		1
    54. 

  54. 

  55. #define clr_TF1			TF1		=		0
    56. 

  56. #define clr_TR1			TR1		=		0
    57. 

  57. #define clr_TF0			TF0		=		0
    58. 

  58. #define clr_TR0			TR0		=		0
    59. 

  59. #define clr_IE1			IE1		=		0
    60. 

  60. #define clr_IT1			IT1		=		0
    61. 

  61. #define clr_IE0			IE0		=		0
    62. 

  62. #define clr_IT0			IT0		=		0
    63. 

  63. 

  64. //**** TMOD		89H **** 
    65. 

  65. #define set_GATE_T1 	TMOD 		|= 	SET_BIT7
    66. 

  66. #define set_CT_T1 		TMOD   	|= 	SET_BIT6
    67. 

  67. #define set_M1_T1 		TMOD  	|= 	SET_BIT5
    68. 

  68. #define set_M0_T1 		TMOD   	|= 	SET_BIT4
    69. 

  69. #define set_GATE_T0 	TMOD 		|= 	SET_BIT3
    70. 

  70. #define set_CT_T0 		TMOD 	  |= 	SET_BIT2
    71. 

  71. #define set_M1_T0 		TMOD   	|= 	SET_BIT1
    72. 

  72. #define set_M0_T0 		TMOD   	|= 	SET_BIT0
    73. 

  73.                             
    74. 

  74. #define clr_GATE_T1 	TMOD 		&= 	~SET_BIT7
    75. 

  75. #define clr_CT_T1 		TMOD   	&= 	~SET_BIT6
    76. 

  76. #define clr_M1_T1 		TMOD   	&= 	~SET_BIT5
    77. 

  77. #define clr_M0_T1 		TMOD   	&= 	~SET_BIT4
    78. 

  78. #define clr_GATE_T0 	TMOD 		&= 	~SET_BIT3
    79. 

  79. #define clr_CT_T0 		TMOD   	&= 	~SET_BIT2
    80. 

  80. #define clr_M1_T0 		TMOD   	&= 	~SET_BIT1
    81. 

  81. #define clr_M0_T0 		TMOD   	&= 	~SET_BIT0
    82. 

  82. 

  83. //**** TH1		8AH **** 
    84. 

  84. //**** TH0		8BH **** 
    85. 

  85. //**** TL1		8CH	**** 
    86. 

  86. //**** TL0		8DH **** 
    87. 

  87. 

  88. //**** CKCON	8EH ****
    89. 

  89. #define set_PWMCKS  CKCON   |= SET_BIT6
    90. 

  90. #define set_T1M     CKCON   |= SET_BIT4
    91. 

  91. #define set_T0M     CKCON   |= SET_BIT3
    92. 

  92. #define set_CLOEN   CKCON   |= SET_BIT1
    93. 

  93.                             
    94. 

  94. #define clr_PWMCKS  CKCON   &= ~SET_BIT6
    95. 

  95. #define clr_T1M     CKCON   &= ~SET_BIT4
    96. 

  96. #define clr_T0M     CKCON   &= ~SET_BIT3
    97. 

  97. #define clr_CLOEN   CKCON   &= ~SET_BIT1
    98. 

  98. 

  99. //**** WKCON	8FH ****
    100. 

  100. #define set_WKTCK   WKCON   |= SET_BIT5
    101. 

  101. #define set_WKTF    WKCON   |= SET_BIT4
    102. 

  102. #define set_WKTR    WKCON   |= SET_BIT3
    103. 

  103. #define set_WKPS2   WKCON   |= SET_BIT2
    104. 

  104. #define set_WKPS1   WKCON   |= SET_BIT1
    105. 

  105. #define set_WKPS0   WKCON   |= SET_BIT0
    106. 

  106.                             
    107. 

  107. #define clr_WKTCK   WKCON   &= ~SET_BIT5
    108. 

  108. #define clr_WKTF    WKCON   &= ~SET_BIT4
    109. 

  109. #define clr_WKTR    WKCON   &= ~SET_BIT3
    110. 

  110. #define clr_WKPS2   WKCON   &= ~SET_BIT2
    111. 

  111. #define clr_WKPS1   WKCON   &= ~SET_BIT1
    112. 

  112. #define clr_WKPS0   WKCON   &= ~SET_BIT0
    113. 

  113. 

  114. /**** P1		90H *****/
    115. 

  115. #define set_P10			P10		=		1
    116. 

  116. #define set_P11			P11		=		1
    117. 

  117. #define set_P12			P12		=		1
    118. 

  118. #define set_P13			P13		=		1
    119. 

  119. #define set_P14			P14		=		1
    120. 

  120. #define set_P15			P15		=		1
    121. 

  121. #define set_P16			P16		=		1
    122. 

  122. #define set_P17			P17		=		1
    123. 

  123. 

  124. #define clr_P10			P10		=		0
    125. 

  125. #define clr_P11			P11		=		0
    126. 

  126. #define clr_P12			P12		=		0
    127. 

  127. #define clr_P13			P13		=		0
    128. 

  128. #define clr_P14			P14		=		0
    129. 

  129. #define clr_P15			P15		=		0
    130. 

  130. #define clr_P16			P16		=		0
    131. 

  131. #define clr_P17			P17		=		0
    132. 

  132. 

  133. //****SFRS		91H ****
    134. 

  134. #define set_SFRPAGE  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=SET_BIT0;EA=BIT_TMP
    135. 

  135. #define clr_SFRPAGE  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS&=~SET_BIT0;EA=BIT_TMP
    136. 

  136. 

  137. //****CAPCON0	92H ****
    138. 

  138. #define set_CAPEN2  CAPCON0 |= SET_BIT6
    139. 

  139. #define set_CAPEN1  CAPCON0 |= SET_BIT5
    140. 

  140. #define set_CAPEN0  CAPCON0 |= SET_BIT4
    141. 

  141. #define set_CAPF2   CAPCON0 |= SET_BIT2
    142. 

  142. #define set_CAPF1   CAPCON0 |= SET_BIT1
    143. 

  143. #define set_CAPF0   CAPCON0 |= SET_BIT0
    144. 

  144. 

  145. #define clr_CAPEN2  CAPCON0 &= ~SET_BIT6
    146. 

  146. #define clr_CAPEN1  CAPCON0 &= ~SET_BIT5
    147. 

  147. #define clr_CAPEN0  CAPCON0 &= ~SET_BIT4
    148. 

  148. #define clr_CAPF2   CAPCON0 &= ~SET_BIT2
    149. 

  149. #define clr_CAPF1   CAPCON0 &= ~SET_BIT1
    150. 

  150. #define clr_CAPF0   CAPCON0 &= ~SET_BIT0
    151. 

  151. 

  152. //**** CAPCON1	93H ****
    153. 

  153. #define set_CAP2LS1 CAPCON1 |= SET_BIT5
    154. 

  154. #define set_CAP2LS0 CAPCON1 |= SET_BIT4
    155. 

  155. #define set_CAP1LS1 CAPCON1 |= SET_BIT3
    156. 

  156. #define set_CAP1LS0 CAPCON1 |= SET_BIT2
    157. 

  157. #define set_CAP0LS1 CAPCON1 |= SET_BIT1
    158. 

  158. #define set_CAP0LS0 CAPCON1 |= SET_BIT0
    159. 

  159. 

  160. #define clr_CAP2LS1 CAPCON1 &= ~SET_BIT5
    161. 

  161. #define clr_CAP2LS0 CAPCON1 &= ~SET_BIT4
    162. 

  162. #define clr_CAP1LS1 CAPCON1 &= ~SET_BIT3
    163. 

  163. #define clr_CAP1LS0 CAPCON1 &= ~SET_BIT2
    164. 

  164. #define clr_CAP0LS1 CAPCON1 &= ~SET_BIT1
    165. 

  165. #define clr_CAP0LS0 CAPCON1 &= ~SET_BIT0
    166. 

  166. 

  167. //**** CAPCON2		94H ****
    168. 

  168. #define set_ENF2  CAPCON2   |= SET_BIT6
    169. 

  169. #define set_ENF1  CAPCON2   |= SET_BIT5
    170. 

  170. #define set_ENF0  CAPCON2   |= SET_BIT4
    171. 

  171.                             
    172. 

  172. #define clr_ENF2  CAPCON2   &= ~SET_BIT6
    173. 

  173. #define clr_ENF1  CAPCON2   &= ~SET_BIT5
    174. 

  174. #define clr_ENF0  CAPCON2   &= ~SET_BIT4
    175. 

  175. 

  176. //**** CKDIV		95H ****
    177. 

  177. 

  178. //**** CKSWT		96H ****  TA protect register
    179. 

  179. #define set_HIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT5;EA=BIT_TMP;
    180. 

  180. #define set_LIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT4;EA=BIT_TMP;
    181. 

  181. #define set_ECLKST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT3;EA=BIT_TMP;
    182. 

  182. #define set_OSC1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT2;EA=BIT_TMP;
    183. 

  183. #define set_OSC0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT1;EA=BIT_TMP;
    184. 

  184. 

  185. #define clr_HIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT5;EA=BIT_TMP;
    186. 

  186. #define clr_LIRCST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT4;EA=BIT_TMP;
    187. 

  187. #define clr_ECLKST  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT3;EA=BIT_TMP;
    188. 

  188. #define clr_OSC1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT2;EA=BIT_TMP;
    189. 

  189. #define clr_OSC0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT1;EA=BIT_TMP;
    190. 

  190. 

  191. //**** CKEN 	97H **** TA protect register
    192. 

  192. #define set_EXTEN1  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT7;EA=BIT_TMP;
    193. 

  193. #define set_EXTEN0  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT6;EA=BIT_TMP;
    194. 

  194. #define set_HIRCEN  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT5;EA=BIT_TMP;
    195. 

  195. #define set_CKSWTF  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT0;EA=BIT_TMP;
    196. 

  196.        
    197. 

  197. #define clr_EXTEN1  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT7;EA=BIT_TMP;
    198. 

  198. #define clr_EXTEN0  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT6;EA=BIT_TMP;
    199. 

  199. #define clr_HIRCEN  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT5;EA=BIT_TMP;
    200. 

  200. #define clr_CKSWTF  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT0;EA=BIT_TMP;
    201. 

  201. 

  202. //**** SCON		98H ****
    203. 

  203. #define set_FE      FE    = 1
    204. 

  204. #define set_SM1     SM1   = 1
    205. 

  205. #define set_SM2     SM2   = 1
    206. 

  206. #define set_REN     REN   = 1
    207. 

  207. #define set_TB8     TB8   = 1
    208. 

  208. #define set_RB8     RB8   = 1
    209. 

  209. #define set_TI      TI    = 1
    210. 

  210. #define set_RI      RI    = 1
    211. 

  211. 

  212. #define clr_FE      FE    = 0
    213. 

  213. #define clr_SM1     SM1   = 0
    214. 

  214. #define clr_SM2     SM2   = 0
    215. 

  215. #define clr_REN     REN   = 0
    216. 

  216. #define clr_TB8     TB8   = 0
    217. 

  217. #define clr_RB8     RB8   = 0
    218. 

  218. #define clr_TI      TI    = 0
    219. 

  219. #define clr_RI      RI    = 0
    220. 

  220. 

  221. //**** SBUF		99H ****
    222. 

  222. //**** SBUF_1	9AH ****
    223. 

  223. 

  224. //**** EIE		9BH ****                      
    225. 

  225. #define set_ET2     EIE     |= SET_BIT7
    226. 

  226. #define set_ESPI    EIE     |= SET_BIT6
    227. 

  227. #define set_EFB     EIE     |= SET_BIT5
    228. 

  228. #define set_EWDT    EIE     |= SET_BIT4
    229. 

  229. #define set_EPWM    EIE     |= SET_BIT3
    230. 

  230. #define set_ECAP    EIE     |= SET_BIT2
    231. 

  231. #define set_EPI     EIE     |= SET_BIT1
    232. 

  232. #define set_EI2C    EIE     |= SET_BIT0
    233. 

  233.                             
    234. 

  234. #define clr_ET2     EIE     &= ~SET_BIT7
    235. 

  235. #define clr_ESPI    EIE     &= ~SET_BIT6
    236. 

  236. #define clr_EFB     EIE     &= ~SET_BIT5
    237. 

  237. #define clr_EWDT    EIE     &= ~SET_BIT4
    238. 

  238. #define clr_EPWM    EIE     &= ~SET_BIT3
    239. 

  239. #define clr_ECAP    EIE     &= ~SET_BIT2
    240. 

  240. #define clr_EPI     EIE     &= ~SET_BIT1
    241. 

  241. #define clr_EI2C    EIE     &= ~SET_BIT0
    242. 

  242. 

  243. //**** EIE1		9CH ****                      
    244. 

  244. #define set_EWKT    EIE1    |= SET_BIT2
    245. 

  245. #define set_ET3     EIE1    |= SET_BIT1
    246. 

  246. #define set_ES_1    EIE1    |= SET_BIT0
    247. 

  247.                             
    248. 

  248. #define clr_EWKT    EIE1    &= ~SET_BIT2
    249. 

  249. #define clr_ET3     EIE1    &= ~SET_BIT1
    250. 

  250. #define clr_ES_1    EIE1    &= ~SET_BIT0
    251. 

  251.                             
    252. 

  252. //**** CHPCON		9DH ****  TA protect register
    253. 

  253. #define set_SWRST   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT7 ;EA=BIT_TMP;
    254. 

  254. #define set_IAPFF   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT6 ;EA=BIT_TMP;
    255. 

  255. #define set_BS      BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT1 ;EA=BIT_TMP;
    256. 

  256. #define set_IAPEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT0 ;EA=BIT_TMP;
    257. 

  257.        
    258. 

  258. #define clr_SWRST   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT7;EA=BIT_TMP;
    259. 

  259. #define clr_IAPFF   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT6;EA=BIT_TMP;
    260. 

  260. #define clr_BS      BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT1;EA=BIT_TMP;
    261. 

  261. #define clr_IAPEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT0;EA=BIT_TMP;
    262. 

  262. 

  263. //**** P2		A0H ****
    264. 

  264. 

  265. //**** AUXR1	A2H ****
    266. 

  266. #define set_SWRF    AUXR1   |= SET_BIT7
    267. 

  267. #define set_RSTPINF AUXR1   |= SET_BIT6
    268. 

  268. #define set_HARDF  	AUXR1   |= SET_BIT5
    269. 

  269. #define set_GF2     AUXR1   |= SET_BIT3
    270. 

  270. #define set_UART0PX AUXR1   |= SET_BIT2
    271. 

  271. #define set_DPS     AUXR1   |= SET_BIT0
    272. 

  272.                             
    273. 

  273. #define clr_SWRF    AUXR1   &= ~SET_BIT7
    274. 

  274. #define clr_RSTPINF AUXR1   &= ~SET_BIT6
    275. 

  275. #define clr_HARDF  	AUXR1   &= ~SET_BIT5
    276. 

  276. #define clr_GF2     AUXR1   &= ~SET_BIT3
    277. 

  277. #define clr_UART0PX AUXR1   &= ~SET_BIT2
    278. 

  278. #define clr_DPS     AUXR1   &= ~SET_BIT0
    279. 

  279. 

  280. //**** BODCON0	A3H ****  TA protect register
    281. 

  281. #define set_BODEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT7;EA=BIT_TMP
    282. 

  282. #define set_BOV2    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT6;EA=BIT_TMP
    283. 

  283. #define set_BOV1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT5;EA=BIT_TMP
    284. 

  284. #define set_BOV0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT4;EA=BIT_TMP
    285. 

  285. #define set_BOF     BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT3;EA=BIT_TMP
    286. 

  286. #define set_BORST   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT2;EA=BIT_TMP
    287. 

  287. #define set_BORF    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT1;EA=BIT_TMP
    288. 

  288. #define set_BOS     BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT0;EA=BIT_TMP
    289. 

  289. 

  290. #define clr_BODEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT7;EA=BIT_TMP
    291. 

  291. #define clr_BOV2    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT6;EA=BIT_TMP
    292. 

  292. #define clr_BOV1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT5;EA=BIT_TMP
    293. 

  293. #define clr_BOV0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT4;EA=BIT_TMP
    294. 

  294. #define clr_BOF     BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT3;EA=BIT_TMP
    295. 

  295. #define clr_BORST   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT2;EA=BIT_TMP
    296. 

  296. #define clr_BORF    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT1;EA=BIT_TMP
    297. 

  297. #define clr_BOS     BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT0;EA=BIT_TMP
    298. 

  298. 

  299. //**** IAPTRG		A4H	****  TA protect register
    300. 

  300. #define set_IAPGO   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG|=SET_BIT0 ;EA=BIT_TMP
    301. 

  301. #define clr_IAPGO   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG&=~SET_BIT0;EA=BIT_TMP
    302. 

  302. 

  303. //**** IAPUEN		A5H **** TA protect register
    304. 

  304. #define set_CFUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT2;EA=BIT_TMP
    305. 

  305. #define set_LDUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT1;EA=BIT_TMP
    306. 

  306. #define set_APUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT0;EA=BIT_TMP
    307. 

  307. 

  308. #define clr_CFUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT2;EA=BIT_TMP
    309. 

  309. #define clr_LDUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT1;EA=BIT_TMP
    310. 

  310. #define clr_APUEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT0;EA=BIT_TMP
    311. 

  311. 

  312. //**** IAPAL	A6H ****
    313. 

  313. //**** IAPAH	A7H ****
    314. 

  314. 

  315. //**** IE			A8H ****
    316. 

  316. #define set_EA      EA       = 1
    317. 

  317. #define set_EADC    EADC     = 1
    318. 

  318. #define set_EBOD    EBOD     = 1
    319. 

  319. #define set_ES      ES       = 1
    320. 

  320. #define set_ET1     ET1      = 1
    321. 

  321. #define set_EX1     EX1      = 1
    322. 

  322. #define set_ET0     ET0      = 1
    323. 

  323. #define set_EX0     EX0      = 1
    324. 

  324. 

  325. #define clr_EA      EA       = 0
    326. 

  326. #define clr_EADC    EADC     = 0
    327. 

  327. #define clr_EBOD    EBOD     = 0
    328. 

  328. #define clr_ES      ES       = 0
    329. 

  329. #define clr_ET1     ET1      = 0
    330. 

  330. #define clr_EX1     EX1      = 0
    331. 

  331. #define clr_ET0     ET0      = 0
    332. 

  332. #define clr_EX0     EX0      = 0
    333. 

  333. 

  334. //**** SADDR		A9H ****
    335. 

  335. 

  336. //**** WDCON		AAH **** TA protect register
    337. 

  337. #define set_WDTR   	BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT7;EA=BIT_TMP;
    338. 

  338. #define set_WDCLR   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT6;EA=BIT_TMP;
    339. 

  339. #define set_WDTF    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT5;EA=BIT_TMP;
    340. 

  340. #define set_WIDPD		BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT4;EA=BIT_TMP;
    341. 

  341. #define set_WDTRF   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT3;EA=BIT_TMP;
    342. 

  342. #define set_WPS2    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT2;EA=BIT_TMP;
    343. 

  343. #define set_WPS1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT1;EA=BIT_TMP;
    344. 

  344. #define set_WPS0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT0;EA=BIT_TMP;
    345. 

  345.         
    346. 

  346. #define clr_WDTEN   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT7;EA=BIT_TMP;
    347. 

  347. #define clr_WDCLR   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT6;EA=BIT_TMP;
    348. 

  348. #define clr_WDTF    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT5;EA=BIT_TMP;
    349. 

  349. #define clr_WDTRF   BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT3;EA=BIT_TMP;
    350. 

  350. #define clr_WPS2    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT2;EA=BIT_TMP;
    351. 

  351. #define clr_WPS1    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT1;EA=BIT_TMP;
    352. 

  352. #define clr_WPS0    BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT0;EA=BIT_TMP;
    353. 

  353. 

  354. //**** BODCON1 ABH **** TA protect register
    355. 

  355. #define set_LPBOD1  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT2 ;EA=BIT_TMP;
    356. 

  356. #define set_LPBOD0  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT1 ;EA=BIT_TMP;
    357. 

  357. #define set_BODFLT  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT0 ;EA=BIT_TMP;
    358. 

  358.         
    359. 

  359. #define clr_LPBOD1  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT2;EA=BIT_TMP;
    360. 

  360. #define clr_LPBOD0  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT1;EA=BIT_TMP;
    361. 

  361. #define clr_BODFLT  BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT0;EA=BIT_TMP;
    362. 

  362. 

  363. 

  364. //**** P3M1		ACH PAGE0 ****
    365. 

  365. #define set_P3M1_0  P3M1    |= SET_BIT0
    366. 

  366. #define clr_P3M1_0  P3M1    &= ~SET_BIT0
    367. 

  367. 

  368. //**** P3S		ACH PAGE1 **** SFRS must set as 1 to modify this register  
    369. 

  369. #define set_P3S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    370. 

  370. #define clr_P3S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    371. 

  371. 

  372. //**** P3M2		ADH PAGE0 ****
    373. 

  373. #define set_P3M2_0  P3M2    |= SET_BIT0
    374. 

  374. #define clr_P3M2_0  P3M2    &= ~SET_BIT0
    375. 

  375. 

  376. //**** P3SR		ADH PAGE1 **** SFRS must set as 1 to modify this register  
    377. 

  377. #define set_P3SR_0  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    378. 

  378. #define clr_P3SR_0  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    379. 

  379. 

  380. //**** IAPFD	AEH ****
    381. 

  381. 

  382. //**** IAPCN	AFH ****
    383. 

  383. #define set_FOEN    IAPN    |= SET_BIT5
    384. 

  384. #define set_FCEN    IAPN    |= SET_BIT4
    385. 

  385. #define set_FCTRL3  IAPN    |= SET_BIT3
    386. 

  386. #define set_FCTRL2  IAPN    |= SET_BIT2
    387. 

  387. #define set_FCTRL1  IAPN    |= SET_BIT1
    388. 

  388. #define set_FCTRL0  IAPN    |= SET_BIT0
    389. 

  389.                             
    390. 

  390. #define clr_FOEN    IAPN    &= ~SET_BIT5
    391. 

  391. #define clr_FCEN    IAPN    &= ~SET_BIT4
    392. 

  392. #define clr_FCTRL3  IAPN    &= ~SET_BIT3
    393. 

  393. #define clr_FCTRL2  IAPN    &= ~SET_BIT2
    394. 

  394. #define clr_FCTRL1  IAPN    &= ~SET_BIT1
    395. 

  395. #define clr_FCTRL0  IAPN    &= ~SET_BIT0
    396. 

  396. 

  397. //**** P3		B0H ****
    398. 

  398. #define set_P30     P30      = 1
    399. 

  399. #define clr_P30     P30      = 0
    400. 

  400. 

  401. //**** P0M1	B1H PAGE0 ****
    402. 

  402. #define set_P0M1_7  P0M1    |= SET_BIT7
    403. 

  403. #define set_P0M1_6  P0M1    |= SET_BIT6
    404. 

  404. #define set_P0M1_5  P0M1    |= SET_BIT5 
    405. 

  405. #define set_P0M1_4  P0M1    |= SET_BIT4
    406. 

  406. #define set_P0M1_3  P0M1    |= SET_BIT3
    407. 

  407. #define set_P0M1_2  P0M1    |= SET_BIT2
    408. 

  408. #define set_P0M1_1  P0M1    |= SET_BIT1
    409. 

  409. #define set_P0M1_0  P0M1    |= SET_BIT0
    410. 

  410. 

  411. #define clr_P0M1_7  P0M1    &= ~SET_BIT7
    412. 

  412. #define clr_P0M1_6  P0M1    &= ~SET_BIT6
    413. 

  413. #define clr_P0M1_5  P0M1    &= ~SET_BIT5
    414. 

  414. #define clr_P0M1_4  P0M1    &= ~SET_BIT4
    415. 

  415. #define clr_P0M1_3  P0M1    &= ~SET_BIT3
    416. 

  416. #define clr_P0M1_2  P0M1    &= ~SET_BIT2
    417. 

  417. #define clr_P0M1_1  P0M1    &= ~SET_BIT1
    418. 

  418. #define clr_P0M1_0  P0M1    &= ~SET_BIT0
    419. 

  419. 

  420. //**** P0S	B2H PAGE1 **** SFRS must set as 1 to modify this register  
    421. 

  421. #define set_P0S_7   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    422. 

  422. #define set_P0S_6   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    423. 

  423. #define set_P0S_5   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    424. 

  424. #define set_P0S_4   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    425. 

  425. #define set_P0S_3   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    426. 

  426. #define set_P0S_2   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    427. 

  427. #define set_P0S_1   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    428. 

  428. #define set_P0S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    429. 

  429. 

  430. #define clr_P0S_7   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    431. 

  431. #define clr_P0S_6   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    432. 

  432. #define clr_P0S_5   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    433. 

  433. #define clr_P0S_4   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    434. 

  434. #define clr_P0S_3   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    435. 

  435. #define clr_P0S_2   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    436. 

  436. #define clr_P0S_1   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    437. 

  437. #define clr_P0S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    438. 

  438. 

  439. //**** P0M2		B2H PAGE0 ****
    440. 

  440. #define set_P0M2_7  P0M2    |= SET_BIT7
    441. 

  441. #define set_P0M2_6  P0M2    |= SET_BIT6
    442. 

  442. #define set_P0M2_5  P0M2    |= SET_BIT5 
    443. 

  443. #define set_P0M2_4  P0M2    |= SET_BIT4
    444. 

  444. #define set_P0M2_3  P0M2    |= SET_BIT3
    445. 

  445. #define set_P0M2_2  P0M2    |= SET_BIT2
    446. 

  446. #define set_P0M2_1  P0M2    |= SET_BIT1
    447. 

  447. #define set_P0M2_0  P0M2    |= SET_BIT0
    448. 

  448. 

  449. #define clr_P0M2_7  P0M2    &= ~SET_BIT7
    450. 

  450. #define clr_P0M2_6  P0M2    &= ~SET_BIT6
    451. 

  451. #define clr_P0M2_5  P0M2    &= ~SET_BIT5
    452. 

  452. #define clr_P0M2_4  P0M2    &= ~SET_BIT4
    453. 

  453. #define clr_P0M2_3  P0M2    &= ~SET_BIT3
    454. 

  454. #define clr_P0M2_2  P0M2    &= ~SET_BIT2
    455. 

  455. #define clr_P0M2_1  P0M2    &= ~SET_BIT1
    456. 

  456. #define clr_P0M2_0  P0M2    &= ~SET_BIT0
    457. 

  457. 

  458. 

  459. //**** P0SR		B0H PAGE1 **** SFRS must set as 1 to modify this register  
    460. 

  460. #define set_P0SR_7  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    461. 

  461. #define set_P0SR_6  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    462. 

  462. #define set_P0SR_5  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    463. 

  463. #define set_P0SR_4  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    464. 

  464. #define set_P0SR_3  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    465. 

  465. #define set_P0SR_2  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    466. 

  466. #define set_P0SR_1  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    467. 

  467. #define set_P0SR_0  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    468. 

  468. 

  469. #define clr_P0SR_7  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    470. 

  470. #define clr_P0SR_6  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    471. 

  471. #define clr_P0SR_5  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    472. 

  472. #define clr_P0SR_4  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    473. 

  473. #define clr_P0SR_3  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    474. 

  474. #define clr_P0SR_2  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    475. 

  475. #define clr_P0SR_1  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    476. 

  476. #define clr_P0SR_0  BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    477. 

  477. 

  478. 

  479. //**** P1M1	B3H PAGE0 ****
    480. 

  480. #define set_P1M1_7  P1M1	|= SET_BIT7
    481. 

  481. #define set_P1M1_6  P1M1	|= SET_BIT6
    482. 

  482. #define set_P1M1_5  P1M1	|= SET_BIT5 
    483. 

  483. #define set_P1M1_4  P1M1	|= SET_BIT4
    484. 

  484. #define set_P1M1_3  P1M1	|= SET_BIT3
    485. 

  485. #define set_P1M1_2  P1M1	|= SET_BIT2
    486. 

  486. #define set_P1M1_1  P1M1	|= SET_BIT1
    487. 

  487. #define set_P1M1_0  P1M1	|= SET_BIT0
    488. 

  488. 

  489. #define clr_P1M1_7  P1M1	&= ~SET_BIT7
    490. 

  490. #define clr_P1M1_6  P1M1	&= ~SET_BIT6
    491. 

  491. #define clr_P1M1_5  P1M1	&= ~SET_BIT5
    492. 

  492. #define clr_P1M1_4  P1M1	&= ~SET_BIT4
    493. 

  493. #define clr_P1M1_3  P1M1	&= ~SET_BIT3
    494. 

  494. #define clr_P1M1_2  P1M1	&= ~SET_BIT2
    495. 

  495. #define clr_P1M1_1  P1M1	&= ~SET_BIT1
    496. 

  496. #define clr_P1M1_0  P1M1	&= ~SET_BIT0
    497. 

  497. 

  498. //**** P1S B3H PAGE1 **** SFRS must set as 1 to modify this register  
    499. 

  499. #define set_P1S_7		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    500. 

  500. #define set_P1S_6		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    501. 

  501. #define set_P1S_5		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    502. 

  502. #define set_P1S_4		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    503. 

  503. #define set_P1S_3		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    504. 

  504. #define set_P1S_2   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    505. 

  505. #define set_P1S_1   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    506. 

  506. #define set_P1S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    507. 

  507. 

  508. #define clr_P1S_7		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    509. 

  509. #define clr_P1S_6		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    510. 

  510. #define clr_P1S_5		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    511. 

  511. #define clr_P1S_4		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    512. 

  512. #define clr_P1S_3		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    513. 

  513. #define clr_P1S_2   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    514. 

  514. #define clr_P1S_1   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    515. 

  515. #define clr_P1S_0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    516. 

  516. 

  517. //**** P1M2		B4H PAGE0 ****                      
    518. 

  518. #define set_P12UP   P1M2    |= SET_BIT2
    519. 

  519. #define set_P1M2_1  P1M2    |= SET_BIT1
    520. 

  520. #define set_P1M2_0  P1M2    |= SET_BIT0
    521. 

  521.                             
    522. 

  522. #define clr_P12UP   P1M2    &= ~SET_BIT2
    523. 

  523. #define clr_P1M2_1  P1M2    &= ~SET_BIT1
    524. 

  524. #define clr_P1M2_0  P1M2    &= ~SET_BIT0
    525. 

  525. 

  526. //**** P1SR		B4H PAGE1 **** SFRS must set as 1 to modify this register  
    527. 

  527. #define set_P1SR_7		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    528. 

  528. #define set_P1SR_6		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    529. 

  529. #define set_P1SR_5		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    530. 

  530. #define set_P1SR_4		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    531. 

  531. #define set_P1SR_3		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    532. 

  532. #define set_P1SR_2		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    533. 

  533. #define set_P1SR_1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    534. 

  534. #define set_P1SR_0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    535. 

  535. 

  536. #define clr_P1SR_7		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    537. 

  537. #define clr_P1SR_6		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    538. 

  538. #define clr_P1SR_5		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    539. 

  539. #define clr_P1SR_4		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    540. 

  540. #define clr_P1SR_3		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    541. 

  541. #define clr_P1SR_2		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    542. 

  542. #define clr_P1SR_1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    543. 

  543. #define clr_P1SR_0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    544. 

  544. 

  545. 

  546. //**** P2S		B5H	****
    547. 

  547. #define set_P2S_0   P2S     |= SET_BIT0
    548. 

  548. #define clr_P2S_0   P2S     &= ~SET_BIT0
    549. 

  549. 

  550. //**** IPH    B7H PAGE0 ****                    
    551. 

  551. #define set_PADCH   IPH		|= SET_BIT6
    552. 

  552. #define set_PBODH   IPH		|= SET_BIT5
    553. 

  553. #define set_PSH     IPH		|= SET_BIT4
    554. 

  554. #define set_PT1H    IPH		|= SET_BIT3
    555. 

  555. #define set_PX11    IPH		|= SET_BIT2
    556. 

  556. #define set_PT0H    IPH		|= SET_BIT1
    557. 

  557. #define set_PX0H    IPH		|= SET_BIT0
    558. 

  558.                             
    559. 

  559. #define clr_PADCH   IPH		&= ~SET_BIT6
    560. 

  560. #define clr_PBODH   IPH		&= ~SET_BIT5
    561. 

  561. #define clr_PSH     IPH		&= ~SET_BIT4
    562. 

  562. #define clr_PT1H    IPH		&= ~SET_BIT3
    563. 

  563. #define clr_PX11    IPH		&= ~SET_BIT2
    564. 

  564. #define clr_PT0H    IPH		&= ~SET_BIT1
    565. 

  565. #define clr_PX0H    IPH		&= ~SET_BIT0
    566. 

  566. 

  567. //**** PWMINTC B7H PAGE1 **** SFRS must set as 1 to modify this register  
    568. 

  568. #define set_INTTYP1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    569. 

  569. #define set_INTTYP0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    570. 

  570. #define set_INTSEL2		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    571. 

  571. #define set_INTSEL1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    572. 

  572. #define set_INTSEL0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    573. 

  573. 

  574. #define clr_INTTYP1   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    575. 

  575. #define clr_INTTYP0   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    576. 

  576. #define clr_INTSEL2		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    577. 

  577. #define clr_INTSEL1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    578. 

  578. #define clr_INTSEL0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    579. 

  579. 

  580. //**** IP		B8H	****
    581. 

  581. #define set_PADC    PADC     = 1
    582. 

  582. #define set_PBOD    PBOD     = 1
    583. 

  583. #define set_PS      PS       = 1
    584. 

  584. #define set_PT1     PT1      = 1
    585. 

  585. #define set_PX1     PX1      = 1
    586. 

  586. #define set_PT0     PT0      = 1
    587. 

  587. #define set_PX0     PX0      = 1
    588. 

  588. 

  589. #define clr_PADC    PADC     = 0
    590. 

  590. #define clr_PBOD    PBOD     = 0
    591. 

  591. #define clr_PS      PS       = 0
    592. 

  592. #define clr_PT1     PT1      = 0
    593. 

  593. #define clr_PX1     PX1      = 0
    594. 

  594. #define clr_PT0     PT0      = 0
    595. 

  595. #define clr_PX0     PX0      = 0
    596. 

  596. 

  597. //**** SADEN		B9H ****
    598. 

  598. //**** SADEN_1	8AH ****
    599. 

  599. //**** SADDR_1	BBH ****
    600. 

  600. //**** I2DAT		BCH ****
    601. 

  601. //**** I2STAT		BDH ****
    602. 

  602. //**** I2CLK		BEH ****
    603. 

  603. 

  604. //**** I2TOC		BFH ****
    605. 

  605. #define set_I2TOCEN		I2TOC		|= SET_BIT2
    606. 

  606. #define set_DIV				I2TOC		|= SET_BIT1
    607. 

  607. #define set_I2TOF			I2TOC		|= SET_BIT0
    608. 

  608. 

  609. #define clr_I2TOCEN		I2TOC		&= ~SET_BIT2
    610. 

  610. #define clr_DIV				I2TOC		&= ~SET_BIT1
    611. 

  611. #define clr_I2TOF			I2TOC		&= ~SET_BIT0
    612. 

  612. 

  613. //**** I2CON  C0H **** 
    614. 

  614. #define set_I2CEN   	I2CEN		= 1
    615. 

  615. #define set_STA     	STA			= 1
    616. 

  616. #define set_STO				STO			= 1
    617. 

  617. #define set_SI				SI			= 1
    618. 

  618. #define set_AA				AA			= 1
    619. 

  619. #define set_I2CPX			I2CPX		= 1
    620. 

  620. 

  621. #define clr_I2CEN			I2CEN		= 0
    622. 

  622. #define clr_STA				STA			= 0
    623. 

  623. #define clr_STO				STO			= 0
    624. 

  624. #define clr_SI				SI			= 0
    625. 

  625. #define clr_AA				AA			= 0
    626. 

  626. #define clr_I2CPX			I2CPX		= 0 
    627. 

  627. 

  628. //**** I2ADDR		C1H ****
    629. 

  629. #define set_GC      I2ADDR  |= SET_BIT0
    630. 

  630. #define clr_GC      I2ADDR  &= ~SET_BIT0
    631. 

  631. 

  632. //**** ADCRL		C2H ****
    633. 

  633. //**** ADCRH		C3H ****
    634. 

  634. 

  635. //**** T3CON		C4H	PAGE0 ****                     
    636. 

  636. #define set_SMOD_1  T3CON   |= SET_BIT7
    637. 

  637. #define set_SMOD0_1 T3CON   |= SET_BIT6
    638. 

  638. #define set_BRCK    T3CON   |= SET_BIT5
    639. 

  639. #define set_TF3     T3CON   |= SET_BIT4
    640. 

  640. #define set_TR3     T3CON   |= SET_BIT3
    641. 

  641. #define set_T3PS2   T3CON   |= SET_BIT2
    642. 

  642. #define set_T3PS1   T3CON   |= SET_BIT1
    643. 

  643. #define set_T3PS0   T3CON   |= SET_BIT0
    644. 

  644.                             
    645. 

  645. #define clr_SMOD_1  T3CON   &= ~SET_BIT7
    646. 

  646. #define clr_SMOD0_1 T3CON   &= ~SET_BIT6
    647. 

  647. #define clr_BRCK    T3CON   &= ~SET_BIT5
    648. 

  648. #define clr_TF3     T3CON   &= ~SET_BIT4
    649. 

  649. #define clr_TR3     T3CON   &= ~SET_BIT3
    650. 

  650. #define clr_T3PS2   T3CON   &= ~SET_BIT2
    651. 

  651. #define clr_T3PS1   T3CON   &= ~SET_BIT1
    652. 

  652. #define clr_T3PS0   T3CON   &= ~SET_BIT0
    653. 

  653. 

  654. //**** PWM4H	C4H	PAGE1 **** SFRS must set as 1 to modify this register  
    655. 

  655. //**** RL3		C5H PAGE0 ****
    656. 

  656. //**** PWM5H	C5H PAGE1 **** SFRS must set as 1 to modify this register  
    657. 

  657. //**** RH3		C6H PAGE0 ****
    658. 

  658. 

  659. //**** PIOCON1 C6H PAGE1 **** SFRS must set as 1 to modify this register  
    660. 

  660. #define set_PIO15		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    661. 

  661. #define set_PIO13   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    662. 

  662. #define set_PIO12   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    663. 

  663. #define set_PIO11   BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    664. 

  664. 

  665. #define clr_PIO15		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    666. 

  666. #define clr_PIO13		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    667. 

  667. #define clr_PIO12		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    668. 

  668. #define clr_PIO11		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    669. 

  669. 

  670. //**** T2CON  C8H ****
    671. 

  671. #define set_TF2     TF2      = 1
    672. 

  672. #define set_TR2     TR2      = 1
    673. 

  673. #define set_CMRL2   CMRL2    = 1
    674. 

  674. 

  675. #define clr_TF2     TF2      = 0
    676. 

  676. #define clr_TR2     TR2      = 0
    677. 

  677. #define clr_CMRL2   CMRL2    = 0
    678. 

  678. 

  679. //**** T2MOD	C9H ****                     
    680. 

  680. #define set_LDEN    T2MOD   |= SET_BIT7
    681. 

  681. #define set_T2DIV2  T2MOD   |= SET_BIT6
    682. 

  682. #define set_T2DIV1  T2MOD   |= SET_BIT5
    683. 

  683. #define set_T2DIV0  T2MOD   |= SET_BIT4
    684. 

  684. #define set_CAPCR   T2MOD   |= SET_BIT3
    685. 

  685. #define set_CMPCR   T2MOD   |= SET_BIT2
    686. 

  686. #define set_LDTS1   T2MOD   |= SET_BIT1
    687. 

  687. #define set_LDTS0   T2MOD   |= SET_BIT0
    688. 

  688.                             
    689. 

  689. #define clr_LDEN    T2MOD   &= ~SET_BIT7
    690. 

  690. #define clr_T2DIV2  T2MOD   &= ~SET_BIT6
    691. 

  691. #define clr_T2DIV1  T2MOD   &= ~SET_BIT5
    692. 

  692. #define clr_T2DIV0  T2MOD   &= ~SET_BIT4
    693. 

  693. #define clr_CAPCR   T2MOD   &= ~SET_BIT3
    694. 

  694. #define clr_CMPCR   T2MOD   &= ~SET_BIT2
    695. 

  695. #define clr_LDTS1   T2MOD   &= ~SET_BIT1
    696. 

  696. #define clr_LDTS0   T2MOD   &= ~SET_BIT0
    697. 

  697. 

  698. //**** RCMP2H CAH ****
    699. 

  699. //**** RCMP2L CBH ****
    700. 

  700. //**** TL2		CCH PAGE0 ****
    701. 

  701. //**** PWM4L 	CCH PAGE1 **** SFRS must set as 1 to modify this register  
    702. 

  702. //**** TH2		CDH PAGE0 ****
    703. 

  703. //**** PWM5L	CDH PAGE1 **** SFRS must set as 1 to modify this register  
    704. 

  704. //**** ADCMPL	CEH **** 
    705. 

  705. //**** ADCMPH	CFH ****
    706. 

  706. 

  707. /****  PSW 		D0H ****/
    708. 

  708. #define set_CY   	CY	= 1
    709. 

  709. #define set_AC		AC  = 1
    710. 

  710. #define set_F0    F0	= 1 
    711. 

  711. #define set_RS1		RS1 = 1
    712. 

  712. #define set_RS0		RS0 = 1
    713. 

  713. #define set_OV		OV 	= 1
    714. 

  714. #define set_P			P		= 1
    715. 

  715. 

  716. #define clr_CY   	CY	= 0
    717. 

  717. #define clr_AC		AC  = 0
    718. 

  718. #define clr_F0    F0	= 0 
    719. 

  719. #define clr_RS1		RS1 = 0
    720. 

  720. #define clr_RS0		RS0 = 0
    721. 

  721. #define clr_OV		OV 	= 0
    722. 

  722. #define clr_P			P		= 0
    723. 

  723. 

  724. //**** PWMPH		D1H ****
    725. 

  725. //**** PWM0H		D2H ****
    726. 

  726. //**** PWM1H		D3H ****
    727. 

  727. //**** PWM2H		D4H ****
    728. 

  728. //**** PWM3H		D5H	****
    729. 

  729. 

  730. //**** PNP			D6H ****
    731. 

  731. #define set_PNP5    PNP     |= SET_BIT5
    732. 

  732. #define set_PNP4    PNP     |= SET_BIT4
    733. 

  733. #define set_PNP3    PNP     |= SET_BIT3
    734. 

  734. #define set_PNP2    PNP     |= SET_BIT2
    735. 

  735. #define set_PNP1    PNP     |= SET_BIT1
    736. 

  736. #define set_PNP0    PNP     |= SET_BIT0
    737. 

  737. 

  738. #define clr_PNP5    PNP     &= ~SET_BIT5
    739. 

  739. #define clr_PNP4    PNP     &= ~SET_BIT4
    740. 

  740. #define clr_PNP3    PNP     &= ~SET_BIT3
    741. 

  741. #define clr_PNP2    PNP     &= ~SET_BIT2
    742. 

  742. #define clr_PNP1    PNP     &= ~SET_BIT1
    743. 

  743. #define clr_PNP0    PNP     &= ~SET_BIT0
    744. 

  744. 

  745. //**** FBD		D7H ****
    746. 

  746. #define set_FBF     FBD     |= SET_BIT7
    747. 

  747. #define set_FBINLS  FBD     |= SET_BIT6
    748. 

  748. #define set_FBD5    FBD     |= SET_BIT5
    749. 

  749. #define set_FBD4    FBD     |= SET_BIT4
    750. 

  750. #define set_FBD3    FBD     |= SET_BIT3
    751. 

  751. #define set_FBD2    FBD     |= SET_BIT2
    752. 

  752. #define set_FBD1    FBD     |= SET_BIT1
    753. 

  753. #define set_FBD0    FBD     |= SET_BIT0
    754. 

  754. 

  755. #define clr_FBF     FBD     &= ~SET_BIT7
    756. 

  756. #define clr_FBINLS  FBD     &= ~SET_BIT6
    757. 

  757. #define clr_FBD5    FBD     &= ~SET_BIT5
    758. 

  758. #define clr_FBD4    FBD     &= ~SET_BIT4
    759. 

  759. #define clr_FBD3    FBD     &= ~SET_BIT3
    760. 

  760. #define clr_FBD2    FBD     &= ~SET_BIT2
    761. 

  761. #define clr_FBD1    FBD     &= ~SET_BIT1
    762. 

  762. #define clr_FBD0    FBD     &= ~SET_BIT0
    763. 

  763. 

  764. /**** PWMCON0			D8H ****/
    765. 

  765. #define set_PWMRUN  PWMRUN   = 1
    766. 

  766. #define set_LOAD    LOAD     = 1
    767. 

  767. #define set_PWMF    PWMF     = 1
    768. 

  768. #define set_CLRPWM  CLRPWM   = 1
    769. 

  769. 

  770. #define clr_PWMRUN  PWMRUN   = 0
    771. 

  771. #define clr_LOAD    LOAD     = 0
    772. 

  772. #define clr_PWMF    PWMF     = 0 
    773. 

  773. #define clr_CLRPWM  CLRPWM   = 0
    774. 

  774. 

  775. //**** PWMPL		D9H ****
    776. 

  776. //**** PWM0L		DAH ****
    777. 

  777. //**** PWM1L		DBH ****
    778. 

  778. //**** PWM2L		DCH ****
    779. 

  779. //**** PWM3L		DDH ****
    780. 

  780. 

  781. //**** PIOCON0	DEH ****
    782. 

  782. #define set_PIO05    PIOCON0     |= SET_BIT5
    783. 

  783. #define set_PIO04    PIOCON0     |= SET_BIT4
    784. 

  784. #define set_PIO03    PIOCON0     |= SET_BIT3
    785. 

  785. #define set_PIO02    PIOCON0     |= SET_BIT2
    786. 

  786. #define set_PIO01    PIOCON0     |= SET_BIT1
    787. 

  787. #define set_PIO00    PIOCON0     |= SET_BIT0
    788. 

  788. 

  789. #define clr_PIO05    PIOCON0     &= ~SET_BIT5
    790. 

  790. #define clr_PIO04    PIOCON0     &= ~SET_BIT4
    791. 

  791. #define clr_PIO03    PIOCON0     &= ~SET_BIT3
    792. 

  792. #define clr_PIO02    PIOCON0     &= ~SET_BIT2
    793. 

  793. #define clr_PIO01    PIOCON0     &= ~SET_BIT1
    794. 

  794. #define clr_PIO00    PIOCON0     &= ~SET_BIT0
    795. 

  795. 

  796. //**** PWMCON1	DFH ****
    797. 

  797. #define set_PWMMOD1		PWMCON1  |= SET_BIT7
    798. 

  798. #define set_PWMMOD0		PWMCON1  |= SET_BIT6
    799. 

  799. #define set_GP      	PWMCON1  |= SET_BIT5
    800. 

  800. #define set_PWMTYP  	PWMCON1  |= SET_BIT4
    801. 

  801. #define set_FBINEN		PWMCON1  |= SET_BIT3
    802. 

  802. #define set_PWMDIV2		PWMCON1  |= SET_BIT2 
    803. 

  803. #define set_PWMDIV1		PWMCON1  |= SET_BIT1
    804. 

  804. #define set_PWMDIV0		PWMCON1  |= SET_BIT0
    805. 

  805.                             
    806. 

  806. #define clr_PWMMOD1		PWMCON1  &= ~SET_BIT7
    807. 

  807. #define clr_PWMMOD0		PWMCON1  &= ~SET_BIT6
    808. 

  808. #define clr_GP				PWMCON1  &= ~SET_BIT5
    809. 

  809. #define clr_PWMTYP		PWMCON1  &= ~SET_BIT4
    810. 

  810. #define clr_FBINEN		PWMCON1  &= ~SET_BIT3
    811. 

  811. #define clr_PWMDIV2		PWMCON1  &= ~SET_BIT2 
    812. 

  812. #define clr_PWMDIV1		PWMCON1  &= ~SET_BIT1
    813. 

  813. #define clr_PWMDIV0		PWMCON1  &= ~SET_BIT0
    814. 

  814. 

  815. //**** ACC	E0H ****
    816. 

  816. 

  817. //**** ADCCON1	E1H ****
    818. 

  818. #define set_STADCPX ADCCON1  |= SET_BIT6
    819. 

  819. #define set_ETGTYP1 ADCCON1  |= SET_BIT3
    820. 

  820. #define set_ETGTYP0 ADCCON1  |= SET_BIT2
    821. 

  821. #define set_ADCEX   ADCCON1  |= SET_BIT1
    822. 

  822. #define set_ADCEN   ADCCON1  |= SET_BIT0
    823. 

  823. 

  824. #define clr_STADCPX ADCCON1  &= ~SET_BIT6
    825. 

  825. #define clr_ETGTYP1 ADCCON1  &= ~SET_BIT3
    826. 

  826. #define clr_ETGTYP0 ADCCON1  &= ~SET_BIT2
    827. 

  827. #define clr_ADCEX   ADCCON1  &= ~SET_BIT1
    828. 

  828. #define clr_ADCEN   ADCCON1  &= ~SET_BIT0
    829. 

  829. 

  830. //**** ADCON2		E2H ****
    831. 

  831. #define set_ADFBEN  ADCCON2  |= SET_BIT7
    832. 

  832. #define set_ADCMPOP ADCCON2  |= SET_BIT6
    833. 

  833. #define set_ADCMPEN ADCCON2  |= SET_BIT5
    834. 

  834. #define set_ADCMPO  ADCCON2  |= SET_BIT4
    835. 

  835. 

  836. #define clr_ADFBEN  ADCCON2  &= ~SET_BIT7
    837. 

  837. #define clr_ADCMPOP ADCCON2  &= ~SET_BIT6
    838. 

  838. #define clr_ADCMPEN ADCCON2  &= ~SET_BIT5
    839. 

  839. #define clr_ADCMPO  ADCCON2  &= ~SET_BIT4
    840. 

  840. 

  841. //**** ADCDLY		E3H ****
    842. 

  842. //**** C0L			E4H ****
    843. 

  843. //**** C0H			E5H ****
    844. 

  844. //**** C1L			E6H ****
    845. 

  845. //**** C1H			E7H ****
    846. 

  846. 

  847. //**** ADCCON0	EAH ****
    848. 

  848. #define set_ADCF    ADCF     = 1
    849. 

  849. #define set_ADCS    ADCS     = 1
    850. 

  850. #define set_ETGSEL1 ETGSEL1  = 1
    851. 

  851. #define set_ETGSEL0 ETGSEL0  = 1
    852. 

  852. #define set_ADCHS3  ADCHS3   = 1
    853. 

  853. #define set_ADCHS2  ADCHS2   = 1
    854. 

  854. #define set_ADCHS1  ADCHS1   = 1
    855. 

  855. #define set_ADCHS0  ADCHS0   = 1
    856. 

  856. 

  857. #define clr_ADCF    ADCF     = 0
    858. 

  858. #define clr_ADCS    ADCS     = 0
    859. 

  859. #define clr_ETGSEL1 ETGSEL1  = 0
    860. 

  860. #define clr_ETGSEL0 ETGSEL0  = 0
    861. 

  861. #define clr_ADCHS3  ADCHS3   = 0
    862. 

  862. #define clr_ADCHS2  ADCHS2   = 0
    863. 

  863. #define clr_ADCHS1  ADCHS1   = 0
    864. 

  864. #define clr_ADCHS0  ADCHS0   = 0
    865. 

  865. 

  866. //**** PICON	E9H	****
    867. 

  867. #define set_PIT67   PICON   |= SET_BIT7
    868. 

  868. #define set_PIT45   PICON   |= SET_BIT6
    869. 

  869. #define set_PIT3    PICON   |= SET_BIT5
    870. 

  870. #define set_PIT2    PICON   |= SET_BIT4
    871. 

  871. #define set_PIT1    PICON   |= SET_BIT3
    872. 

  872. #define set_PIT0    PICON   |= SET_BIT2
    873. 

  873. #define set_PIPS1   PICON   |= SET_BIT1
    874. 

  874. #define set_PIPS0   PICON   |= SET_BIT0
    875. 

  875.                             
    876. 

  876. #define clr_PIT67   PICON   &= ~SET_BIT7
    877. 

  877. #define clr_PIT45   PICON   &= ~SET_BIT6
    878. 

  878. #define clr_PIT3    PICON   &= ~SET_BIT5
    879. 

  879. #define clr_PIT2    PICON   &= ~SET_BIT4
    880. 

  880. #define clr_PIT1    PICON   &= ~SET_BIT3
    881. 

  881. #define clr_PIT0    PICON   &= ~SET_BIT2
    882. 

  882. #define clr_PIPS1   PICON   &= ~SET_BIT1
    883. 

  883. #define clr_PIPS0   PICON   &= ~SET_BIT0
    884. 

  884. 

  885. //**** PINEN		EAH **** 
    886. 

  886. #define set_PINEN7  PINEN   |= SET_BIT7
    887. 

  887. #define set_PINEN6  PINEN   |= SET_BIT6
    888. 

  888. #define set_PINEN5  PINEN   |= SET_BIT5
    889. 

  889. #define set_PINEN4  PINEN   |= SET_BIT4
    890. 

  890. #define set_PINEN3  PINEN   |= SET_BIT3
    891. 

  891. #define set_PINEN2  PINEN   |= SET_BIT2
    892. 

  892. #define set_PINEN1  PINEN   |= SET_BIT1
    893. 

  893. #define set_PINEN0  PINEN   |= SET_BIT0
    894. 

  894.                             
    895. 

  895. #define clr_PINEN7  PINEN   &= ~SET_BIT7
    896. 

  896. #define clr_PINEN6  PINEN   &= ~SET_BIT6
    897. 

  897. #define clr_PINEN5  PINEN   &= ~SET_BIT5
    898. 

  898. #define clr_PINEN4  PINEN   &= ~SET_BIT4
    899. 

  899. #define clr_PINEN3  PINEN   &= ~SET_BIT3
    900. 

  900. #define clr_PINEN2  PINEN   &= ~SET_BIT2
    901. 

  901. #define clr_PINEN1  PINEN   &= ~SET_BIT1
    902. 

  902. #define clr_PINEN0  PINEN   &= ~SET_BIT0
    903. 

  903.                             
    904. 

  904. //**** PIPEN 		EBH ****
    905. 

  905. #define set_PIPEN7  PIPEN   |= SET_BIT7
    906. 

  906. #define set_PIPEN6  PIPEN   |= SET_BIT6
    907. 

  907. #define set_PIPEN5  PIPEN   |= SET_BIT5
    908. 

  908. #define set_PIPEN4  PIPEN   |= SET_BIT4
    909. 

  909. #define set_PIPEN3  PIPEN   |= SET_BIT3
    910. 

  910. #define set_PIPEN2  PIPEN   |= SET_BIT2
    911. 

  911. #define set_PIPEN1  PIPEN   |= SET_BIT1
    912. 

  912. #define set_PIPEN0  PIPEN   |= SET_BIT0
    913. 

  913.                             
    914. 

  914. #define clr_PIPEN7  PIPEN   &= ~SET_BIT7
    915. 

  915. #define clr_PIPEN6  PIPEN   &= ~SET_BIT6
    916. 

  916. #define clr_PIPEN5  PIPEN   &= ~SET_BIT5
    917. 

  917. #define clr_PIPEN4  PIPEN   &= ~SET_BIT4
    918. 

  918. #define clr_PIPEN3  PIPEN   &= ~SET_BIT3
    919. 

  919. #define clr_PIPEN2  PIPEN   &= ~SET_BIT2
    920. 

  920. #define clr_PIPEN1  PIPEN   &= ~SET_BIT1
    921. 

  921. #define clr_PIPEN0  PIPEN   &= ~SET_BIT0
    922. 

  922.    
    923. 

  923. //**** PIF	ECH ****
    924. 

  924. #define set_PIF7    PIF     |= SET_BIT7
    925. 

  925. #define set_PIF6    PIF     |= SET_BIT6
    926. 

  926. #define set_PIF5    PIF     |= SET_BIT5
    927. 

  927. #define set_PIF4    PIF     |= SET_BIT4
    928. 

  928. #define set_PIF3    PIF     |= SET_BIT3
    929. 

  929. #define set_PIF2    PIF     |= SET_BIT2
    930. 

  930. #define set_PIF1    PIF     |= SET_BIT1
    931. 

  931. #define set_PIF0    PIF     |= SET_BIT0
    932. 

  932. 

  933. #define clr_PIF7    PIF     &= ~SET_BIT7
    934. 

  934. #define clr_PIF6    PIF     &= ~SET_BIT6
    935. 

  935. #define clr_PIF5    PIF     &= ~SET_BIT5
    936. 

  936. #define clr_PIF4    PIF     &= ~SET_BIT4
    937. 

  937. #define clr_PIF3    PIF     &= ~SET_BIT3
    938. 

  938. #define clr_PIF2    PIF     &= ~SET_BIT2
    939. 

  939. #define clr_PIF1    PIF     &= ~SET_BIT1
    940. 

  940. #define clr_PIF0    PIF     &= ~SET_BIT0
    941. 

  941. 

  942. //**** C2L  EDH ****  
    943. 

  943. //**** C2H	EEH ****
    944. 

  944. 

  945. //**** EIP	EFH ****                      
    946. 

  946. #define set_PT2     EIP     |= SET_BIT7
    947. 

  947. #define set_PSPI    EIP     |= SET_BIT6
    948. 

  948. #define set_PFB     EIP     |= SET_BIT5
    949. 

  949. #define set_PWDT    EIP     |= SET_BIT4
    950. 

  950. #define set_PPWM    EIP     |= SET_BIT3
    951. 

  951. #define set_PCAP    EIP     |= SET_BIT2
    952. 

  952. #define set_PPI     EIP     |= SET_BIT1
    953. 

  953. #define set_PI2C    EIP     |= SET_BIT0
    954. 

  954.                             
    955. 

  955. #define clr_PT2     EIP     &= ~SET_BIT7
    956. 

  956. #define clr_PSPI    EIP     &= ~SET_BIT6
    957. 

  957. #define clr_PFB     EIP     &= ~SET_BIT5
    958. 

  958. #define clr_PWDT    EIP     &= ~SET_BIT4
    959. 

  959. #define clr_PPWM    EIP     &= ~SET_BIT3
    960. 

  960. #define clr_PCAP    EIP     &= ~SET_BIT2
    961. 

  961. #define clr_PPI     EIP     &= ~SET_BIT1
    962. 

  962. #define clr_PI2C    EIP     &= ~SET_BIT0
    963. 

  963. 

  964. //**** B	F0H ****
    965. 

  965. 

  966. //**** CAPCON3		F1H ****
    967. 

  967. #define set_CAP13   CAPCON3    |= SET_BIT7
    968. 

  968. #define set_CAP12   CAPCON3    |= SET_BIT6
    969. 

  969. #define set_CAP11   CAPCON3    |= SET_BIT5
    970. 

  970. #define set_CAP10   CAPCON3    |= SET_BIT4
    971. 

  971. #define set_CAP03   CAPCON3    |= SET_BIT3
    972. 

  972. #define set_CAP02   CAPCON3    |= SET_BIT2
    973. 

  973. #define set_CAP01   CAPCON3    |= SET_BIT1
    974. 

  974. #define set_CAP00   CAPCON3    |= SET_BIT0
    975. 

  975. 

  976. #define clr_CAP13   CAPCON3    &= ~SET_BIT7
    977. 

  977. #define clr_CAP12   CAPCON3    &= ~SET_BIT6
    978. 

  978. #define clr_CAP11   CAPCON3    &= ~SET_BIT5
    979. 

  979. #define clr_CAP10   CAPCON3    &= ~SET_BIT4
    980. 

  980. #define clr_CAP03   CAPCON3    &= ~SET_BIT3
    981. 

  981. #define clr_CAP02   CAPCON3    &= ~SET_BIT2
    982. 

  982. #define clr_CAP01   CAPCON3    &= ~SET_BIT1
    983. 

  983. #define clr_CAP00   CAPCON3    &= ~SET_BIT0
    984. 

  984. 

  985. //**** CAPCON4		F2H ****
    986. 

  986. #define set_CAP23    CAPCON4    |= SET_BIT3
    987. 

  987. #define set_CAP22    CAPCON4    |= SET_BIT2
    988. 

  988. #define set_CAP21    CAPCON4    |= SET_BIT1
    989. 

  989. #define set_CAP20    CAPCON4    |= SET_BIT0
    990. 

  990. 

  991. #define clr_CAP23    CAPCON4    &= ~SET_BIT3
    992. 

  992. #define clr_CAP22    CAPCON4    &= ~SET_BIT2
    993. 

  993. #define clr_CAP21    CAPCON4    &= ~SET_BIT1
    994. 

  994. #define clr_CAP20    CAPCON4    &= ~SET_BIT0
    995. 

  995. 

  996. //**** SPCR		F3H PAGE0 ****
    997. 

  997. #define set_SSOE    SPCR    |= SET_BIT7
    998. 

  998. #define set_SPIEN   SPCR    |= SET_BIT6
    999. 

  999. #define set_LSBFE   SPCR    |= SET_BIT5
    1000. 

  1000. #define set_MSTR    SPCR    |= SET_BIT4
    1001. 

  1001. #define set_CPOL    SPCR    |= SET_BIT3
    1002. 

  1002. #define set_CPHA    SPCR    |= SET_BIT2
    1003. 

  1003. #define set_SPR1    SPCR    |= SET_BIT1
    1004. 

  1004. #define set_SPR0    SPCR    |= SET_BIT0
    1005. 

  1005. 

  1006. #define clr_SSOE    SPCR    &= ~SET_BIT7
    1007. 

  1007. #define clr_SPIEN   SPCR    &= ~SET_BIT6
    1008. 

  1008. #define clr_LSBFE   SPCR    &= ~SET_BIT5
    1009. 

  1009. #define clr_MSTR    SPCR    &= ~SET_BIT4
    1010. 

  1010. #define clr_CPOL    SPCR    &= ~SET_BIT3
    1011. 

  1011. #define clr_CPHA    SPCR    &= ~SET_BIT2
    1012. 

  1012. #define clr_SPR1    SPCR    &= ~SET_BIT1
    1013. 

  1013. #define clr_SPR0    SPCR    &= ~SET_BIT0
    1014. 

  1014. 

  1015. //**** SPCR2		F3H PAGE1 **** SFRS must set as 1 to modify this register  
    1016. 

  1016. #define set_SPIS1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    1017. 

  1017. #define set_SPIS0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    1018. 

  1018. 

  1019. #define clr_SPIS1		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    1020. 

  1020. #define clr_SPIS0		BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP
    1021. 

  1021. 

  1022. //**** SPSR			F4H ****
    1023. 

  1023. #define set_SPIF    SPSR    |= SET_BIT7
    1024. 

  1024. #define set_WCOL    SPSR    |= SET_BIT6
    1025. 

  1025. #define set_SPIOVF  SPSR    |= SET_BIT5
    1026. 

  1026. #define set_MODF    SPSR    |= SET_BIT4
    1027. 

  1027. #define set_DISMODF SPSR    |= SET_BIT3
    1028. 

  1028.                             
    1029. 

  1029. #define clr_SPIF    SPSR    &= ~SET_BIT7
    1030. 

  1030. #define clr_WCOL    SPSR    &= ~SET_BIT6
    1031. 

  1031. #define clr_SPIOVF  SPSR    &= ~SET_BIT5
    1032. 

  1032. #define clr_MODF    SPSR    &= ~SET_BIT4
    1033. 

  1033. #define clr_DISMODF SPSR    &= ~SET_BIT3
    1034. 

  1034. 

  1035. //**** SPDR		F5H ****
    1036. 

  1036. 

  1037. //**** AINDIDS	F6H ****
    1038. 

  1038. #define set_P11DIDS AINDIDS  |= SET_BIT7
    1039. 

  1039. #define set_P03DIDS AINDIDS  |= SET_BIT6
    1040. 

  1040. #define set_P04DIDS AINDIDS  |= SET_BIT5
    1041. 

  1041. #define set_P05DIDS AINDIDS  |= SET_BIT4
    1042. 

  1042. #define set_P06DIDS AINDIDS  |= SET_BIT3
    1043. 

  1043. #define set_P07DIDS AINDIDS  |= SET_BIT2
    1044. 

  1044. #define set_P30DIDS AINDIDS  |= SET_BIT1
    1045. 

  1045. #define set_P17DIDS AINDIDS  |= SET_BIT0
    1046. 

  1046. 

  1047. #define clr_P11DIDS AINDIDS  &= ~SET_BIT7
    1048. 

  1048. #define clr_P03DIDS AINDIDS  &= ~SET_BIT6
    1049. 

  1049. #define clr_P04DIDS AINDIDS  &= ~SET_BIT5
    1050. 

  1050. #define clr_P05DIDS AINDIDS  &= ~SET_BIT4
    1051. 

  1051. #define clr_P06DIDS AINDIDS  &= ~SET_BIT3
    1052. 

  1052. #define clr_P07DIDS AINDIDS  &= ~SET_BIT2
    1053. 

  1053. #define clr_P30DIDS AINDIDS  &= ~SET_BIT1
    1054. 

  1054. #define clr_P17DIDS AINDIDS  &= ~SET_BIT0
    1055. 

  1055. 

  1056. //**** EIPH			F7H ****
    1057. 

  1057. #define set_PT2H    EIPH    |= SET_BIT7
    1058. 

  1058. #define set_PSPIH   EIPH    |= SET_BIT6
    1059. 

  1059. #define set_PFBH    EIPH    |= SET_BIT5
    1060. 

  1060. #define set_PWDTH   EIPH    |= SET_BIT4
    1061. 

  1061. #define set_PPWMH   EIPH    |= SET_BIT3
    1062. 

  1062. #define set_PCAPH   EIPH    |= SET_BIT2
    1063. 

  1063. #define set_PPIH    EIPH    |= SET_BIT1
    1064. 

  1064. #define set_PI2CH   EIPH    |= SET_BIT0
    1065. 

  1065.                             
    1066. 

  1066. #define clr_PT2H    EIPH    &= ~SET_BIT7
    1067. 

  1067. #define clr_PSPIH   EIPH    &= ~SET_BIT6
    1068. 

  1068. #define clr_PFBH    EIPH    &= ~SET_BIT5
    1069. 

  1069. #define clr_PWDTH   EIPH    &= ~SET_BIT4
    1070. 

  1070. #define clr_PPWMH   EIPH    &= ~SET_BIT3
    1071. 

  1071. #define clr_PCAPH   EIPH    &= ~SET_BIT2
    1072. 

  1072. #define clr_PPIH    EIPH    &= ~SET_BIT1
    1073. 

  1073. #define clr_PI2CH   EIPH    &= ~SET_BIT0
    1074. 

  1074. 

  1075. /**** SCON_1		F8H ****/
    1076. 

  1076. #define set_FE_1    FE_1  = 1
    1077. 

  1077. #define set_SM1_1   SM1_1 = 1
    1078. 

  1078. #define set_SM2_1   SM2_1 = 1
    1079. 

  1079. #define set_REN_1   REN_1 = 1
    1080. 

  1080. #define set_TB8_1   TB8_1 = 1
    1081. 

  1081. #define set_RB8_1   RB8_1 = 1
    1082. 

  1082. #define set_TI_1    TI_1  = 1
    1083. 

  1083. #define set_RI_1    RI_1  = 1
    1084. 

  1084. 

  1085. #define clr_FE_1    FE_1  = 0
    1086. 

  1086. #define clr_SM1_1   SM1_1 = 0
    1087. 

  1087. #define clr_SM2_1   SM2_1 = 0
    1088. 

  1088. #define clr_REN_1   REN_1 = 0
    1089. 

  1089. #define clr_TB8_1   TB8_1 = 0
    1090. 

  1090. #define clr_RB8_1   RB8_1 = 0
    1091. 

  1091. #define clr_TI_1    TI_1  = 0
    1092. 

  1092. #define clr_RI_1    RI_1  = 0
    1093. 

  1093. 

  1094. //**** PDTEN		F9H ****
    1095. 

  1095. #define set_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT2  ;EA=BIT_TMP;
    1096. 

  1096. #define set_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT1  ;EA=BIT_TMP;
    1097. 

  1097. #define set_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT0  ;EA=BIT_TMP;
    1098. 

  1098. 

  1099. #define clr_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT2 ;EA=BIT_TMP;
    1100. 

  1100. #define clr_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT1 ;EA=BIT_TMP;
    1101. 

  1101. #define clr_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT0 ;EA=BIT_TMP;
    1102. 

  1102. 

  1103. //**** PDTCNT		FAH ****
    1104. 

  1104. 

  1105. //**** PMEN   	FBH ****                   
    1106. 

  1106. #define set_PMEN5   PMEN    |= SET_BIT5
    1107. 

  1107. #define set_PMEN4   PMEN    |= SET_BIT4
    1108. 

  1108. #define set_PMEN3   PMEN    |= SET_BIT3
    1109. 

  1109. #define set_PMEN2   PMEN    |= SET_BIT2
    1110. 

  1110. #define set_PMEN1   PMEN    |= SET_BIT1
    1111. 

  1111. #define set_PMEN0   PMEN    |= SET_BIT0
    1112. 

  1112.                             
    1113. 

  1113. #define clr_PMEN5   PMEN    &= ~SET_BIT5
    1114. 

  1114. #define clr_PMEN4   PMEN    &= ~SET_BIT4
    1115. 

  1115. #define clr_PMEN3   PMEN    &= ~SET_BIT3
    1116. 

  1116. #define clr_PMEN2   PMEN    &= ~SET_BIT2
    1117. 

  1117. #define clr_PMEN1   PMEN    &= ~SET_BIT1
    1118. 

  1118. #define clr_PMEN0   PMEN    &= ~SET_BIT0
    1119. 

  1119.                             
    1120. 

  1120. //**** PMD		FCH ****                       
    1121. 

  1121. #define set_PMD7    PMD     |= SET_BIT7
    1122. 

  1122. #define set_PMD6    PMD     |= SET_BIT6
    1123. 

  1123. #define set_PMD5    PMD     |= SET_BIT5
    1124. 

  1124. #define set_PMD4    PMD     |= SET_BIT4
    1125. 

  1125. #define set_PMD3    PMD     |= SET_BIT3
    1126. 

  1126. #define set_PMD2    PMD     |= SET_BIT2
    1127. 

  1127. #define set_PMD1    PMD     |= SET_BIT1
    1128. 

  1128. #define set_PMD0    PMD     |= SET_BIT0
    1129. 

  1129.                             
    1130. 

  1130. #define clr_PMD7    PMD     &= ~SET_BIT7
    1131. 

  1131. #define clr_PMD6    PMD     &= ~SET_BIT6
    1132. 

  1132. #define clr_PMD5    PMD     &= ~SET_BIT5
    1133. 

  1133. #define clr_PMD4    PMD     &= ~SET_BIT4
    1134. 

  1134. #define clr_PMD3    PMD     &= ~SET_BIT3
    1135. 

  1135. #define clr_PMD2    PMD     &= ~SET_BIT2
    1136. 

  1136. #define clr_PMD1    PMD     &= ~SET_BIT1
    1137. 

  1137. #define clr_PMD0    PMD     &= ~SET_BIT0
    1138. 

  1138. 

  1139. //****	EIP1 		FEH ****                     
    1140. 

  1140. #define set_PWKT    EIP1    |= SET_BIT2
    1141. 

  1141. #define set_PT3     EIP1    |= SET_BIT1
    1142. 

  1142. #define set_PS_1    EIP1    |= SET_BIT0
    1143. 

  1143.                             
    1144. 

  1144. #define clr_PWKT    EIP1    &= ~SET_BIT2
    1145. 

  1145. #define clr_PT3     EIP1    &= ~SET_BIT1
    1146. 

  1146. #define clr_PS_1    EIP1    &= ~SET_BIT0
    1147. 

  1147. 

  1148. //**** EIPH1		FFH ****                
    1149. 

  1149. #define set_PWKTH   EIPH1   |= SET_BIT2
    1150. 

  1150. #define set_PT3H    EIPH1   |= SET_BIT1
    1151. 

  1151. #define set_PSH_1   EIPH1   |= SET_BIT0
    1152. 

  1152.                             
    1153. 

  1153. #define clr_PWKTH   EIPH1   &= ~SET_BIT2
    1154. 

  1154. #define clr_PT3H    EIPH1   &= ~SET_BIT1
    1155. 

  1155. #define clr_PSH_1   EIPH1   &= ~SET_BIT0
    1156. 

  1156. 

  1157. #endif
    1158. 

  1158.