26dffe234cc5928bde29c040b311ed44285a5f1a.svn-base 6.2 KB

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  1. #ifndef __N76E003_KEIL_H__
  2. #define __N76E003_KEIL_H__
  3. /*--------------------------------------------------------------------------
  4. N76E003.H
  5. Header file for Nuvoton N76E003
  6. --------------------------------------------------------------------------*/
  7. sfr P0 = 0x80;
  8. sfr SP = 0x81;
  9. sfr DPL = 0x82;
  10. sfr DPH = 0x83;
  11. sfr RCTRIM0 = 0x84;
  12. sfr RCTRIM1 = 0x85;
  13. sfr RWK = 0x86;
  14. sfr PCON = 0x87;
  15. sfr TCON = 0x88;
  16. sfr TMOD = 0x89;
  17. sfr TL0 = 0x8A;
  18. sfr TL1 = 0x8B;
  19. sfr TH0 = 0x8C;
  20. sfr TH1 = 0x8D;
  21. sfr CKCON = 0x8E;
  22. sfr WKCON = 0x8F;
  23. sfr P1 = 0x90;
  24. sfr SFRS = 0x91; //TA Protection
  25. sfr CAPCON0 = 0x92;
  26. sfr CAPCON1 = 0x93;
  27. sfr CAPCON2 = 0x94;
  28. sfr CKDIV = 0x95;
  29. sfr CKSWT = 0x96; //TA Protection
  30. sfr CKEN = 0x97; //TA Protection
  31. sfr SCON = 0x98;
  32. sfr SBUF = 0x99;
  33. sfr SBUF_1 = 0x9A;
  34. sfr EIE = 0x9B;
  35. sfr EIE1 = 0x9C;
  36. sfr CHPCON = 0x9F; //TA Protection
  37. sfr P2 = 0xA0;
  38. sfr AUXR1 = 0xA2;
  39. sfr BODCON0 = 0xA3; //TA Protection
  40. sfr IAPTRG = 0xA4; //TA Protection
  41. sfr IAPUEN = 0xA5; //TA Protection
  42. sfr IAPAL = 0xA6;
  43. sfr IAPAH = 0xA7;
  44. sfr IE = 0xA8;
  45. sfr SADDR = 0xA9;
  46. sfr WDCON = 0xAA; //TA Protection
  47. sfr BODCON1 = 0xAB; //TA Protection
  48. sfr P3M1 = 0xAC;
  49. sfr P3S = 0xAC; //Page1
  50. sfr P3M2 = 0xAD;
  51. sfr P3SR = 0xAD; //Page1
  52. sfr IAPFD = 0xAE;
  53. sfr IAPCN = 0xAF;
  54. sfr P3 = 0xB0;
  55. sfr P0M1 = 0xB1;
  56. sfr P0S = 0xB1; //Page1
  57. sfr P0M2 = 0xB2;
  58. sfr P0SR = 0xB2; //Page1
  59. sfr P1M1 = 0xB3;
  60. sfr P1S = 0xB3; //Page1
  61. sfr P1M2 = 0xB4;
  62. sfr P1SR = 0xB4; //Page1
  63. sfr P2S = 0xB5;
  64. sfr IPH = 0xB7;
  65. sfr PWMINTC = 0xB7; //Page1
  66. sfr IP = 0xB8;
  67. sfr SADEN = 0xB9;
  68. sfr SADEN_1 = 0xBA;
  69. sfr SADDR_1 = 0xBB;
  70. sfr I2DAT = 0xBC;
  71. sfr I2STAT = 0xBD;
  72. sfr I2CLK = 0xBE;
  73. sfr I2TOC = 0xBF;
  74. sfr I2CON = 0xC0;
  75. sfr I2ADDR = 0xC1;
  76. sfr ADCRL = 0xC2;
  77. sfr ADCRH = 0xC3;
  78. sfr T3CON = 0xC4;
  79. sfr PWM4H = 0xC4; //Page1
  80. sfr RL3 = 0xC5;
  81. sfr PWM5H = 0xC5; //Page1
  82. sfr RH3 = 0xC6;
  83. sfr PIOCON1 = 0xC6; //Page1
  84. sfr TA = 0xC7;
  85. sfr T2CON = 0xC8;
  86. sfr T2MOD = 0xC9;
  87. sfr RCMP2L = 0xCA;
  88. sfr RCMP2H = 0xCB;
  89. sfr TL2 = 0xCC;
  90. sfr PWM4L = 0xCC; //Page1
  91. sfr TH2 = 0xCD;
  92. sfr PWM5L = 0xCD; //Page1
  93. sfr ADCMPL = 0xCE;
  94. sfr ADCMPH = 0xCF;
  95. sfr PSW = 0xD0;
  96. sfr PWMPH = 0xD1;
  97. sfr PWM0H = 0xD2;
  98. sfr PWM1H = 0xD3;
  99. sfr PWM2H = 0xD4;
  100. sfr PWM3H = 0xD5;
  101. sfr PNP = 0xD6;
  102. sfr FBD = 0xD7;
  103. sfr PWMCON0 = 0xD8;
  104. sfr PWMPL = 0xD9;
  105. sfr PWM0L = 0xDA;
  106. sfr PWM1L = 0xDB;
  107. sfr PWM2L = 0xDC;
  108. sfr PWM3L = 0xDD;
  109. sfr PIOCON0 = 0xDE;
  110. sfr PWMCON1 = 0xDF;
  111. sfr ACC = 0xE0;
  112. sfr ADCCON1 = 0xE1;
  113. sfr ADCCON2 = 0xE2;
  114. sfr ADCDLY = 0xE3;
  115. sfr C0L = 0xE4;
  116. sfr C0H = 0xE5;
  117. sfr C1L = 0xE6;
  118. sfr C1H = 0xE7;
  119. sfr ADCCON0 = 0xE8;
  120. sfr PICON = 0xE9;
  121. sfr PINEN = 0xEA;
  122. sfr PIPEN = 0xEB;
  123. sfr PIF = 0xEC;
  124. sfr C2L = 0xED;
  125. sfr C2H = 0xEE;
  126. sfr EIP = 0xEF;
  127. sfr B = 0xF0;
  128. sfr CAPCON3 = 0xF1;
  129. sfr CAPCON4 = 0xF2;
  130. sfr SPCR = 0xF3;
  131. sfr SPCR2 = 0xF3; //Page1
  132. sfr SPSR = 0xF4;
  133. sfr SPDR = 0xF5;
  134. sfr AINDIDS = 0xF6;
  135. sfr EIPH = 0xF7;
  136. sfr SCON_1 = 0xF8;
  137. sfr PDTEN = 0xF9; //TA Protection
  138. sfr PDTCNT = 0xFA; //TA Protection
  139. sfr PMEN = 0xFB;
  140. sfr PMD = 0xFC;
  141. sfr EIP1 = 0xFE;
  142. sfr EIPH1 = 0xFF;
  143. /* BIT Registers */
  144. /* SCON_1 */
  145. sbit SM0_1 = SCON_1^7;
  146. sbit FE_1 = SCON_1^7;
  147. sbit SM1_1 = SCON_1^6;
  148. sbit SM2_1 = SCON_1^5;
  149. sbit REN_1 = SCON_1^4;
  150. sbit TB8_1 = SCON_1^3;
  151. sbit RB8_1 = SCON_1^2;
  152. sbit TI_1 = SCON_1^1;
  153. sbit RI_1 = SCON_1^0;
  154. /* ADCCON0 */
  155. sbit ADCF = ADCCON0^7;
  156. sbit ADCS = ADCCON0^6;
  157. sbit ETGSEL1 = ADCCON0^5;
  158. sbit ETGSEL0 = ADCCON0^4;
  159. sbit ADCHS3 = ADCCON0^3;
  160. sbit ADCHS2 = ADCCON0^2;
  161. sbit ADCHS1 = ADCCON0^1;
  162. sbit ADCHS0 = ADCCON0^0;
  163. /* PWMCON0 */
  164. sbit PWMRUN = PWMCON0^7;
  165. sbit LOAD = PWMCON0^6;
  166. sbit PWMF = PWMCON0^5;
  167. sbit CLRPWM = PWMCON0^4;
  168. /* PSW */
  169. sbit CY = PSW^7;
  170. sbit AC = PSW^6;
  171. sbit F0 = PSW^5;
  172. sbit RS1 = PSW^4;
  173. sbit RS0 = PSW^3;
  174. sbit OV = PSW^2;
  175. sbit P = PSW^0;
  176. /* T2CON */
  177. sbit TF2 = T2CON^7;
  178. sbit TR2 = T2CON^2;
  179. sbit CM_RL2 = T2CON^0;
  180. /* I2CON */
  181. sbit I2CEN = I2CON^6;
  182. sbit STA = I2CON^5;
  183. sbit STO = I2CON^4;
  184. sbit SI = I2CON^3;
  185. sbit AA = I2CON^2;
  186. sbit I2CPX = I2CON^0;
  187. /* IP */
  188. sbit PADC = IP^6;
  189. sbit PBOD = IP^5;
  190. sbit PS = IP^4;
  191. sbit PT1 = IP^3;
  192. sbit PX1 = IP^2;
  193. sbit PT0 = IP^1;
  194. sbit PX0 = IP^0;
  195. /* P3 */
  196. sbit P30 = P3^0;
  197. /* IE */
  198. sbit EA = IE^7;
  199. sbit EADC = IE^6;
  200. sbit EBOD = IE^5;
  201. sbit ES = IE^4;
  202. sbit ET1 = IE^3;
  203. sbit EX1 = IE^2;
  204. sbit ET0 = IE^1;
  205. sbit EX0 = IE^0;
  206. /* P2 */
  207. sbit P20 = P2^0;
  208. /* SCON */
  209. sbit SM0 = SCON^7;
  210. sbit FE = SCON^7;
  211. sbit SM1 = SCON^6;
  212. sbit SM2 = SCON^5;
  213. sbit REN = SCON^4;
  214. sbit TB8 = SCON^3;
  215. sbit RB8 = SCON^2;
  216. sbit TI = SCON^1;
  217. sbit RI = SCON^0;
  218. /* P1 */
  219. sbit P17 = P1^7;
  220. sbit P16 = P1^6;
  221. sbit TXD_1 = P1^6;
  222. sbit P15 = P1^5;
  223. sbit P14 = P1^4;
  224. sbit SDA = P1^4;
  225. sbit P13 = P1^3;
  226. sbit SCL = P1^3;
  227. sbit P12 = P1^2;
  228. sbit P11 = P1^1;
  229. sbit P10 = P1^0;
  230. /* TCON */
  231. sbit TF1 = TCON^7;
  232. sbit TR1 = TCON^6;
  233. sbit TF0 = TCON^5;
  234. sbit TR0 = TCON^4;
  235. sbit IE1 = TCON^3;
  236. sbit IT1 = TCON^2;
  237. sbit IE0 = TCON^1;
  238. sbit IT0 = TCON^0;
  239. /* P0 */
  240. sbit P07 = P0^7;
  241. sbit RXD = P0^7;
  242. sbit P06 = P0^6;
  243. sbit TXD = P0^6;
  244. sbit P05 = P0^5;
  245. sbit P04 = P0^4;
  246. sbit STADC = P0^4;
  247. sbit P03 = P0^3;
  248. sbit P02 = P0^2;
  249. sbit RXD_1 = P0^2;
  250. sbit P01 = P0^1;
  251. sbit MISO = P0^1;
  252. sbit P00 = P0^0;
  253. sbit MOSI = P0^0;
  254. #endif